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參數(shù)資料
| 型號： | NCP1081DEG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 257K |
| 描述： | IC CONV CTLR POE-PD 40W 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 類型： | 以太網(wǎng)供電開關(guān)（PoE） |
| 應(yīng)用： | 遠(yuǎn)程外設(shè)（工業(yè)控制，相機(jī)，數(shù)據(jù)訪問） |
| 內(nèi)部開關(guān)： | 是 |
| 電流限制： | 1.1A |
| 電源電壓： | 0 V ~ 57 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
NCP1081
http://onsemi.com
5
Table 1. PIN DESCRIPTIONS
Name
Pin No.
Type
Description
VPORTP
1
Supply
Positive input power. Voltage with respect to VPORTN
1,2
.
VPORTN1
VPORTN2
6,8
Ground
Negative input power. Connected to the source of the internal passswitch.
RTN
7
Ground
DCDC controller power return. Connected to the drain of the internal passswitch. It must
be connected to ARTN. This pin is also the drain of the internal passswitch.
ARTN
14
Ground
DCDC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
VDDH
16
Supply
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
VDDL
17
Supply
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external lowpower LED (1 mA max.) connected to nCLASS_AT, and can
also be used to add extra biasing current in the external optocoupler. VDDL must be by-
passed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
CLASS
2
Input
Classification current programming pin. Connect a resistor between CLASS and VPORTN
1,2
.
INRUSH
4
Input
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN
1,2
.
ILIM1
5
Input
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN
1,2
.
UVLO
3
Input
DCDC controller undervoltage lockout input. Voltage with respect to VPORTN
1,2
. Connect
a resistordivider from VPORTP to UVLO to VPORTN
1,2
to set an external UVLO threshold.
GATE
15
Output
DCDC controller gate driver output pin.
OSC
11
Input
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
nCLASS_AT
13
Output,
Open Drain
Activelow, opendrain Layer 1 dualfinger classification indicator.
COMP
18
I/O
Output of the internal error amplifier of the DCDC controller. COMP is pulledup internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
optocoupler. Voltage with respect to ARTN.
FB
19
Input
DCDC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
CS
12
Input
Currentsense input for the DCDC controller. Voltage with respect to ARTN.
SS
20
Input
Softstart input for the DCDC controller. A capacitor between SS and ARTN determines the
softstart timing.
TEST1
9
Input
Digital test pin must always be connected to VPORTN
1,2
.
TEST2
10
Input
Digital test pin must always be connected to VPORTN
1,2
.
EP
Exposed pad. Connected to VPORTN
1,2
ground.
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