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參數(shù)資料
| 型號： | NCP1207-D |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | PWM Current-Mode Controller for Free Running Quasi-Resonant Operation |
| 中文描述： | PWM電流模式控制器上運(yùn)行的免費(fèi)準(zhǔn)諧振操作 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 202K |
| 代理商： | NCP1207-D |
NCP1207
http://onsemi.com
14
Calculating the V
CC
Capacitor
As the above section describes, the fall down sequence
depends upon the V
CC
level: how long does it take for the
V
CC
line to go from 12 V to 10 V The required time depends
on the startup sequence of your system, i.e. when you first
apply the power to the IC. The corresponding transient fault
duration due to the output capacitor charging must be less
than the time needed to discharge from 12 V to 10 V,
otherwise the supply will not properly start. The test consists
in either simulating or measuring in the lab how much time
the system takes to reach the regulation at full load. Let’s
suppose that this time corresponds to 6.0 ms. Therefore a
V
CC
fall time of 10 ms could be well appropriated in order
to not trigger the overload detection circuitry. If the
corresponding IC consumption, including the MOSFET
drive, establishes at 1.8 mA (e.g. with an 11 nC MOSFET),
we can calculate the required capacitor using the following
formula:
t
i
t of 10 ms, C equals 9.0 F or 22 F for a standard value.
When an overload condition occurs, the IC blocks its
internal circuitry and its consumption drops to 330 A
typical. This happens at V
CC
= 10 V and it remains stuck
until V
CC
reaches 5.3 V: we are in latchoff phase. Again,
using the calculated 22 F and 330 A current consumption,
this latchoff phase lasts: 313 ms.
V
C
, with V = 2.0 V. Then for a wanted
HV Pin Recommended Protection
When the user unplugs a power supply built with a QR
controller such as the NCP1207, two phenomena can
appear:
1. A negative ringing can take place on pin8 due to a
resonance between the primary inductance and
the bulk capacitor. As any CMOS device, the
NCP1207 is sensitive to negative voltages that
could appear on it’s pins and could create an
internal latchup condition.
2. When the bulk capacitor discharges, the internal
latch is reset by the voltage developed over the
sense resistor and the
ON
time expands as less
voltage is available. When the highvoltage rail
becomes too low, the gate drives permanently
stays high since no reset occurs. This situation is
not desirable in many applications.
For the above reasons, we strongly recommend to add a
highvoltage diode like a 1N4007 between the bulk
capacitor and the V
CC
pin. When the bulk level collapses, it
naturally shuts the controller down and eradicates the two
above problems.
Figure 29.
D1
1N4007
8
7
6
5
1
2
3
4
Cbulk
+
NCP1207
+
HV
Operation Shots
Below are some oscilloscope shots captured at
V
in
= 120 VDC with a transformer featuring a 800 H
primary inductance.
Figure 30.
This plot gathers waveforms captured at three different
operating points:
1
st
upper plot: free run, valley switching operation,
P
out
= 26 W
2
nd
middle plot: min T
off
clamps the switching frequency
and selects the second valley
3
rd
lowest plot: the skip slices the second valley pattern
and will further expand the burst as P
out
goes low
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