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參數(shù)資料
型號(hào): NCP1217D100R2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Enhanced PWM Current−Mode Controller for High−Power Universal Off−Line Supplies
中文描述: 0.5 A SWITCHING CONTROLLER, 110 kHz SWITCHING FREQ-MAX, PDSO8
封裝: LEAD FREE, SOIC-8
文件頁數(shù): 10/18頁
文件大小: 249K
代理商: NCP1217D100R2G
NCP1217, NCP1217A
http://onsemi.com
10
Figure 18. Typical Waveforms in Short Circuit Conditions
VCC
ON
= 12.8 V
V
CC
DRIVING PULSES
VCC
min
= 7.6 V
VCC
latch
= 5.6 V
Calculating the V
CC
Capacitor
The V
CC
capacitor can be calculated knowing the IC
consumption as soon as V
CC
reaches 12.8 V. Suppose that a
NCP1217P065 is used and drives a MOSFET with a 30 nC
total gate charge (Qg). The total average current is thus
made of ICC1 (750
A) plus the driver current,
Fsw * Qg
1.95 mA
. The total current is therefore 2.7 mA.
The V available to fully startup the circuit (e.g. never reach
the 8.2 V VCC
min
during power on) is
13.78.2
best case or 4.9 V worse case
(11.97.0)
. We have a
capacitor that then needs to supply the NCP1217 with
2.7 mA during a given time until the auxiliary supply takes
over. Suppose that this time was measured at around 15 ms.
CV
CC
is calculated using the equation
C
C
8.3 F.
Select a 22 F/25 V and this will fit.
5.5 V
t · i
V
or
Skipping Cycle Mode
The NCP1217 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level (Vpin 1), the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 20).
Suppose we have the following component values:
Lp, primary inductance = 350 H
Fsw, switching frequency = 65 kHz
Ip skip = 600 mA (or 333 mV/Rsense)
The
2· Lp · Ip2· Fsw
mode with a bunch length of 10 ms over a recurrent
period of 100 ms, then the total power transfer is:
4.1 * 0.1
410 mW
.
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight.
theoretical
power
transfer
is
therefore:
1
4.1 W
. If this IC enters skip cycle
Figure 19.
SKIP CYCLE OPERATION
I
P(min)
= 333 mV/R
SENSE
NORMAL CURRENT
MODE OPERATION
FB
1 V
4.2 V, FB Pin Open
3.2 V, Upper
Dynamic Range
Time
When FB is above the skip cycle threshold (1.0 V by
default), the peak current cannot exceed 1.0 V/Rsense.
When the IC enters the skip cycle mode, the peak current
cannot go below Vpin1/3.3. The user still has the flexibility
to alter this 1.0 V by either shunting pin 1 to ground through
a resistor or raising it through a resistor up to the desired
level. In this later case, care must be taken to keep sufficient
margin between this pin 1 adjustment level and the latchoff
level. Grounding pin 1 permanently invalidates the skip
cycle operation.
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相關(guān)代理商/技術(shù)參數(shù)
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