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參數(shù)資料
| 型號： | NCP1560HDR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Quadruple Differential Line Receiver With 3-State Outputs 16-PDIP 0 to 70 |
| 中文描述： | 0.01 A SWITCHING CONTROLLER, 516 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | SOP-16 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大小： | 122K |
| 代理商： | NCP1560HDR2 |
NCP1560
http://onsemi.com
16
Maximum Duty Cycle
A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to V
DC(inv)
. If the
FF Ramp voltage exceeds V
DC(inv)
, the output of the Max
DC Comparator goes high.
This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
Duty cycle is defined as:
ton
T
Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
V
DC(inv)
in a time equal to t
on(max)
as shown in Figure 33.
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DC
MAX
, which
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
DC
ton
f
Figure 33. Maximum ON Time Limit Waveforms
Oscillator Ramp
0 V
0 V
FF Ramp
T
t
on(max)
V
DC(inv)
2 V
An internal resistor divider from a 2.0 V reference is used
to set V
DC(inv)
. If the DC
MAX
pin is grounded, V
DC(inv)
is
0.88 V. If the pin is floating, V
DC(inv)
is 1.19 V. This is
equivalent to 60% or 80% of a 1.5 V FF Ramp. V
DC(inv)
can
be adjusted to other values by using an external resistor
network on the DC
MAX
pin. For example, if the minimum
line voltage is 36 V, R
FF
is 434 k , operating frequency is
300 kHz and a maximum duty cycle of 70% is required,
V
DC(inv)
is calculated as follows:
IFF
CFF
VDC(inv)
6.7 k
ton(max)
125 k
VDC(inv)
88.2 A
6.7 k
2.33 s
10 pF
125 k
1.10 V
This can be achieved by connecting a 45.3 k resistor
from the DC
MAX
pin to GND. The maximum duty cycle
limit can be disabled connecting a 100 k resistor between
the DC
MAX
and V
REF
pins.
5.0 V Reference
The NCP1560 includes a precision 5.0 V reference output.
The reference output is biased directly from V
AUX
and it can
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV within the specified operating range.
It is recommended to bypass the reference output with a
0.1 F ceramic capacitor. The reference output is disabled
when an UV fault is present.
PWM Comparator
The output of an external error amplifier is compared to
the FF Ramp by means of the PWM Comparator. The
external error amplifier drives the V
EA
input. There is a
0.7 V offset between the V
EA
input and the PWM
Comparator inverting input. The offset is provided by a
series diode and resistor. If the voltage on the V
EA
input is
below 0.7 V, the outputs are disabled.
The PWM Comparator controls the duty cycle by turning
OFF the outputs once the FF Ramp voltage exceeds the
offset V
EA
voltage. The V
EA
range required to control the
DC from 0% to DC
MAX
is given by the equation below:
VEA(L)
VEA
IFF
186.56 pf
DC
f
VEA(L)
where, V
EA(L)
is the PWM comparator lower input
threshold.
Soft Start
Soft start (SS) allows the converter to gradually reach
steady state operation, thus reducing start-up stress and
surges on the system. The duty cycle is limited during a soft
start sequence by comparing the Oscillator Ramp to the SS
voltage (V
SS
) by means of the Soft Start Comparator.
A 6.2 A current source starts to charge the capacitor on
the SS pin once faults are removed and V
AUX
reaches 11 V.
The Soft Start Comparator controls the duty cycle while the
SS voltage is below 2.0 V. Once V
SS
reaches 2.0 V, it exceeds
the Oscillator Ramp voltage and the Soft Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the soft start
voltage.
Figure 34. Soft Start Timing Diagram
OUT1
OUT2
V
SS
Oscillator
Ramp
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