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參數資料
| 型號： | NCP1562A |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | High Performance Active Active Clamp/Reset PWM Controller Controller(高性能有效Clamp/Reset PWM控制器) |
| 中文描述： | 高性能主動有源鉗位/復位PWM控制器控制器（高性能有效鉗位/復位的PWM控制器） |
| 文件頁數： | 20/26頁 |
| 文件大小： | 277K |
| 代理商： | NCP1562A |
NCP1562A, NCP1562B
http://onsemi.com
20
The minimum value of R
FF
is determined by the FF
Ramp discharge current (I
FF(D)
). The current through R
FF
(I
RFF
) should be at least ten times smaller than I
FF(D)
for a
sharp FF Ramp transition. Equations 3 and 4 are used to
determine R
FF
and C
FF
.
Vin
0.1
IFF(D)
RFF
(eq. 3)
CFF
D
ln
Vin
Vin-3V
f
RFF
(eq. 4)
where,
f
is the operating frequency. It is recommended to
bias the FF circuit with enough current to provide good
noise immunity.
PWM Comparator
In steady state operation, the PWM Comparator adjusts
the duty cycle by comparing the error signal to the FF
Ramp. The error signal is fed into the V
EA
pin. The V
EA
pin
can be driven directly with an optocoupler without the need
of an external pullup resistor as shown in Figure 45. In
some instances, it may be required to have a pullup resistor
smaller than the internal resistor (R4) to adjust the gain of
the isolation stage. This is easily accomplished by
connecting an external resistor (R
EA
) in parallel with R4.
R
EA
is connected between the V
REF
and V
EA
pins. The
effective pullup resistance is the parallel combination of
R4 and R
EA
.
PWM
Comparator
+
-
+
-
0.2 V
270 k
2 k
V
REF
R
EA
(Optional)
V
EA
FF
Feedback
Signal
FF Ramp
3 V
0 V
Figure 45. Optocoupler Driving V
EA
Input
20 k
The drive of the V
EA
pin is simplified by internally
incorporating a series diode and resistor. The series diode
provides a 0.7 V offset between the V
EA
input and the
PWM Comparator inverting input. It allows reaching zero
duty cycle without the need of pulling the V
EA
pin all the
way to GND. The outputs are enabled if the V
EA
voltage is
approximately 0.5 V above the valley of the FF Ramp.
Outputs
The NCP1562 has two in-phase output drivers with an
adjustable overlap delay (t
D
). The main output, OUT1, has
a source resistance of 4.0 (typ) and a sink resistance of
2.5
(typ). The secondary output, OUT2, has a source and
a sink resistance of 12
(typ). OUT1 is rated at a
maximum of 2.0 A and OUT2 is rated at a maximum of
1.0 A. If a higher drive capability is required, an external
driver stage can be easily added as shown in Figure 46.
V
AUX
Output
Figure 46. Discrete Boost Drive Stage
OUT1
or
OUT2
OUT1 drives the main MOSFET, and OUT2 drives a low
side P-Channel active clamp MOSFET. A high side
N-Channel active clamp MOSFET or a synchronous
rectifier can also be driven by inverting OUT2. OUT2 is
purposely sized smaller than OUT1 because the active
clamp MOSFET only sees the magnetizing current.
Therefore, a smaller active clamp MOSFET with less input
capacitance can be used compared to the main switch.
Once V
AUX
reaches V
AUX(on)
(typically 10.3 V), the
internal startup circuit is disabled and the outputs are
enabled if no faults are present. Otherwise, the outputs
remain disabled until the fault is removed and V
AUX
reaches V
AUX(on)
. The outputs are disabled after a soft-stop
sequence if V
AUX
is below V
AUX(on)
or if V
AUX
reaches
7.0 V.
The outputs are biased directly from V
AUX
and their high
state voltage is approximately V
AUX
. Therefore, the
auxiliary supply voltage should not exceed the maximum
gate voltage of the main or active clamp MOSFET.
The high current drive capability of the outputs will
generate inductance-induced spikes if inductance is not
reduced on the outputs. This can be done by reducing the
connection length between the drivers and their loads and
using wide connections.
Overlap Delay
The overlap delay prevents simultaneous conduction of
the main and active clamp MOSFETs. The secondary
output, OUT2, precedes OUT1 during a low to high
transition and trails OUT1 during a high to low transition.
Figure 47 shows the relationship between OUT1 and
OUT2.
t
D
(Leading)
OUT1
OUT2
t
D
(Trailing)
Figure 47. Output Timing Diagram
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相關代理商/技術參數 |
參數描述 |
|---|---|
| NCP1562A WAF | 制造商:ON Semiconductor 功能描述: |
| NCP1562ADBR2G | 功能描述:電壓模式 PWM 控制器 HI PERF RESET PWM CONTLR RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| NCP1562ADR2G | 功能描述:電壓模式 PWM 控制器 HI PERF RESET PWM CONTLR RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| NCP1562BDBR2G | 功能描述:電壓模式 PWM 控制器 HI PERF RESET PWM CONTLR RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| NCP1562BDR2G | 功能描述:電壓模式 PWM 控制器 HI PERF RESET PWM CONTLR RoHS:否 制造商:Texas Instruments 輸出端數量:1 拓撲結構:Buck 輸出電壓:34 V 輸出電流: 開關頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
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