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參數(shù)資料
| 型號(hào)： | NCP1562B |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | High Performance Active Active Clamp/Reset PWM Controller Controller(高性能有效Active Clamp/Reset PWM控制器) |
| 中文描述： | 高性能主動(dòng)有源鉗位/復(fù)位PWM控制器控制器（高性能有效有源鉗位/復(fù)位的PWM控制器） |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 277K |
| 代理商： | NCP1562B |
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NCP1562A, NCP1562B
http://onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin
Symbol
Description
1
V
in
Connect the input line voltage directly to this pin to enable the internal startup regulator. A constant
current source supplies current from this pin to the capacitor connected to the V
AUX
pin, eliminating the
need for a startup resistor. The charge current is typically 10 mA. Maximum input voltage is 100 V.
2
UVOV
Input supply voltage is scaled down and sampled by means of a resistor divider. The same pin is used
for both undervoltage (UV) and overvoltage (OV) detection using a novel architecture (patent pending).
The minimum and maximum input supply voltage thresholds are adjusted independently. A UV
condition exists if the UVOV voltage is below 2.0 V and an OV condition exists if the UVOV voltage
exceeds 3.0 V. The undervoltage threshold is trimmed during manufacturing to obtain
allowing a tighter power stage design. Both the UV and OV detectors have a 100 mV hysteresis.
3% accuracy
3
FF
An external R-C divider from the input line generates the Feedforward Ramp. This ramp is used by the
PWM comparator to set the duty cycle, thus providing direct line regulation. An internal pulldown
transistor discharges the external capacitor every cycle. Once discharged, the capacitor is effectively
grounded until the next cycle begins.
4
CS
Overcurrent sense input. If the CS voltage exceeds 0.2 V (or 0.5 V in the NCP1562B) the converter
operates in cycle-by-cycle current limit. Once a current limit pulse is detected, the cycle skip timer is
enabled. Internal leading edge blanking pulse prevents nuisance triggering during normal operation.
The leading edge blanking is disabled during soft-start and output overload conditions to improve the
response to faults.
5
GND
Control circuit ground. All control and timing components that connect to GND should have the shortest
loop possible to this pin to improve noise immunity.
6
R
T
C
T
An external R
T
-C
T
divider from V
REF
sets the operating frequency and maximum duty cycle of OUT1.
The maximum operating frequency is 1.0 MHz. A sawtooth Ramp between 2.0 V and 3.0 V is
generated by sequentially charging and discharging C
T
. The peak and valley of the Ramp are
accurately controlled to provide precise control of the duty cycle and frequency. The outputs are
disabled during the C
T
discharge time.
7
SYNC
Proprietary bidirectional frequency synchronization architecture allows two NCP1562 devices to
synchronize together. The lower frequency device becomes the slave. It can also synchronize to an
external signal.
8
V
REF
Precision 5.0 V reference. Maximum output current is 5.0 mA. It is required to bypass the reference
with a capacitor. The recommended capacitance range is between 0.047 F and 1.0 F.
9
V
EA
The error signal from an external error amplifier is fed to this input and compared to the Feedforward
Ramp. A series diode and resistor offset the voltage on this pin before it is applied to the PWM
Comparator inverting input. An internal pullup resistor allows direct connection to an optocoupler.
10
SS
A 10 A current source charges the external capacitor connected to this pin. Duty cycle is limited
during startup by comparing the voltage on this pin to the Feedforward Ramp. Under steady state
conditions, the SS voltage is approximately 3.8 V. Once a UV, OV, overtemperature or cycle skip fault
is detected, the SS capacitor is discharged in a controlled manner with a 100 A current source. The
duty cycle is then slowly reduced until reaching 0%.
11
t
D
An external resistor between this pin and GND sets the overlap time delay between OUT1 and OUT2
transitions.
12
CSKIP
The converter is disabled if a continuous overcurrent condition exists. The time to determine the fault
and the time the converter is disabled are programmed by the capacitor (C
CSKIP
) connected to this pin.
The cycle skip timer is enabled after a current limit fault is detected. Once enabled, C
CSKIP
is charged
with a 100 A source. If the overcurrent fault is removed before entering the soft-stop mode, the
capacitor is discharged with a 10 A source. Once C
CSKIP
reaches 3.0 V, the converter enters a
soft-stop mode and C
CSKIP
is discharged with a 10 A source. The converter is re-enabled once
C
CSKIP
reaches 0.5 V. If the condition resulting in overcurrent is cleared during this phase, C
CSKIP
discharges to 0 V. Otherwise, it starts charging from 0.5 V, setting up a hiccup mode operation.
13
OUT2
Secondary output of the PWM Controller. It can be used to drive an active clamp/reset switch, a
synchronous rectifier topology, or both. OUT2 has an adjustable leading and trailing edge overlap delay
against OUT1. OUT2 has source and sink resistances of 12 (typ.). OUT2 is designed to handle up
to 1.0 A.
14
PGND
Ground connection for OUT1 and OUT2. Tie to the power stage return with a short loop.
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