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| 型號： | NCP1607BDR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 17/23頁 |
| 文件大小： | 255K |
| 描述： | IC PFC CONTROLLER CRM 8SOIC |
| 標準包裝： | 1 |
| 模式： | 臨界傳導（CRM） |
| 電流 - 啟動： | 23.5µA |
| 電源電壓： | 9.5 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOICN |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1607BDR2GOSDKR |
NCP1607
http://onsemi.com
17
STATIC OVERVOLTAGE PROTECTION
If the OVP condition lasts for a long time, it may happen
that the error amplifier output reaches its minimum level
(i.e. Control = V
EAL
). It would then not be able to sink any
current and maintain the OVP fault. Therefore, to avoid any
discontinuity in the OVP disabling effect, the circuit
incorporates a comparator which detects when the lower
level of the error amplifier is reached. This event, called
static OVP , disables the output drives. Once the OVP
event is over, and the output voltage has dropped to normal,
then Control rises above the lower limit and the driver is
reenabled (Figure 35).
Figure 35. OVP Timing Diagram
Dynamic OVP
Static OVP
DRV
I
OVPH
I
OVPL
V
EAH
V
CONTROL
V
OUT
V
EAL
I
CONTROL
NCP1607 Undervoltage Protection (UVP)
When the PFC stage is plugged in, the output voltage is
forced to roughly equate the peak line voltage. The
NCP1607 detects an undervoltage fault when this output
voltage is unusually low, such that the feedback voltage is
below V
UVP
(300 mV typical). In an UVP fault, the drive
output and error amplifier (EA) are disabled. The latter is
done so that the EA does not source a current which would
increase the FB voltage and prevent the UVP event from
being accurately detected. The UVP feature helps to
protect the application if something is wrong with the
power path to the bulk capacitor (i.e. the capacitor cannot
charge up) or if the controller cannot sense the bulk voltage
(i.e. the feedback loop is open).
Furthermore, the NCP1607 incorporates a novel startup
sequence which ensures that undervoltage conditions are
always detected at startup. It accomplishes this by waiting
approximately 180 ms after V
CC
reaches V
CC(on)
before
enabling the error amplifier (Figure 36). During this wait
time, it looks to see if the feedback (FB) voltage is greater
than the UVP threshold. If not, then the controller enters a
UVP fault and leaves the error amplifier disabled.
However, if the FB pin voltage increases and exceeds the
UVP level, then the controller will start the application up
normally.
Figure 36. The NCP1607s Startup Sequence with
and without a UVP Fault
FB
Control
2.5 V
UVP
UVP Wait
UVP Wait
V
UVP
V
EAH
V
EAL
V
OUT
V
OUT
V
CC(off)
V
CC(on)
V
CC
UVP Fault is Removed
The voltage on the output which exits a UVP fault is
given by:
V
OUT(UVP)
+
R
OUT1
) R
EQ
R
EQ
@ V
UVP
(eq. 15)
If R
OUT1
= 4 MW and R
EQ
= 25.16 kW, then the V
OUT
UVP threshold is 48 V. This corresponds to an input voltage
of approximately 34 Vac.
Open Feedback Loop Protection
The NCP1607 features comprehensive protection
against open feedback loop conditions by including OVP,
UVP, and Floating Pin Protection (FPP). Figure 37
illustrates three conditions in which the feedback loop is
open. The corresponding number below describes each
condition shown in Figure 37.
1. UVP Protection: The connection from resistor
R
OUT1
to the FB pin is open. R
OUT2
pulls down
the FB pin to ground. The UVP comparator
detects a UVP fault and the drive is disabled.
2. OVP Protection: The connection from resistor
R
OUT2
to the FB pin is open. R
OUT1
pulls up the
FB pin to the output voltage. The ESD diode
clamps the FB voltage to 10 V and R
OUT1
limits
the current into the FB pin. The V
EAL
clamp
detects a static OVP fault and the drive is
disabled.
3. FPP Protection: The FB pin is floating. The
internal pulldown resistor R
FB
pulls down the FB
voltage below the UVP threshold. The UVP
comparator detects a UVP fault and the drive is
disabled.
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