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參數資料
| 型號： | NCT214MT3R2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 3/19頁 |
| 文件大小： | 284K |
| 描述： | IC TEMP SENSOR LOC/REM 10WDFN |
| 標準包裝： | 3,000 |
| 功能： | 溫度監控系統（傳感器） |
| 傳感器類型： | 內部和外部 |
| 感應溫度： | 0°C ~ 127°C，-64°C ~ 191°C |
| 精確度： | ±2.5°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | 2 線串行，I²C?/SMBUS? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 10-WDFN（3x3） |
| 包裝： | 帶卷 (TR) |
NCT214
http://onsemi.com
3
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
Positive Supply Voltage (V
DD
) to GND
0.3, +3.6
V
D+
0.3 to V
DD
+ 0.3
V
D to GND
0.3 to +0.6
V
SCLK, SDATA, ALERT
, THERM
0.3 to +3.6
V
Input Current, SDATA, THERM
1, +50
mA
Input Current, D
?
mA
ESD Rating, All Pins (Human Body Model)
1,500
V
Maximum Junction Temperature (T
J
MAX
)
150
癈
Storage Temperature Range
65 to +150
癈
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
Table 3. THERMAL CHARACTERISTICS (Note 1)
Package Type
q
JA
q
JC
Unit
10-lead WDFN
142
43.74
癈/W
1. q
JA
is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.
Table 4. SMBus/I
2
C TIMING SPECIFICATIONS (Note 1)
Parameter
Limit at T
MIN
and T
MAX
Unit
Description
f
SCLK
400
kHz max
t
LOW
1.3
ms min
Clock Low Period, between 10% Points
t
HIGH
0.6
ms min
Clock High Period, between 90% Points
t
R
300
ns max
Clock/Data Rise Time
t
F
300
ns max
Clock/Data Fall Time
t
SU;
STA
600
ns min
Start Condition Setup Time
t
HD;
STA
(Note 2)
600
ns min
Start Condition Hold Time
t
SU;
DAT
(Note 3)
100
ns min
Data Setup Time
t
SU;
STO
(Note 4)
600
ns min
Stop Condition Setup Time
t
BUF
1.3
ms min
Bus Free Time between Stop and Start Conditions
1. Guaranteed by design, but not production tested.
2. Time from 10% of SDATA to 90% of SCLK.
3. Time for 10% or 90% of SDATA to 10% of SCLK.
4. Time for 90% of SCLK to 10% of SDATA.
Figure 2. Serial Bus Timing
STOP
START
t
SU; DAT
t
HIGH
t
F
t
HD; DAT
t
R
t
LOW
t
SU; STO
STOP START
SCLK
SDATA
t
BUF
t
HD; STA
t
HD; STA
t
SU; STA
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