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參數資料
| 型號： | NCV8881PWR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 26/33頁 |
| 文件大小： | 321K |
| 描述： | IC REG TRPL BUCK/LINEAR 16SOIC |
| 標準包裝： | 1 |
| 拓撲： | 降壓（降壓）（1），線性（LDO）（2） |
| 功能： | 車載 |
| 輸出數： | 3 |
| 頻率 - 開關： | 170kHz |
| 電壓/電流 - 輸出 1： | 3.3 V ~ 8 V，1.5A |
| 電壓/電流 - 輸出 2： | 5V，100mA |
| 電壓/電流 - 輸出 3： | 8.5V，40mA |
| 帶 LED 驅動器： | 無 |
| 帶監控器： | 無 |
| 帶序列發生器： | 無 |
| 電源電壓： | 5 V ~ 19 V |
| 工作溫度： | -40°C ~ 150°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬）裸露焊盤 |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 標準包裝 |
| 其它名稱： | NCV8881PWR2GOSDKR |
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NCV8881
http://onsemi.com
26
0
8P5
1
2
3
4
5
6
7
9
10
11
12
OUTPUT
ENABLE
5P0
VIN
8
SMPS
SOFTSTART TIMER
ShortCircuit Threshold
SMPS LATCHED OFF
Regulation Threshold
Figure 51. SMPS ShortCircuit After Successful Startup #2
WATCHDOG
WATCHDOG FUNCTION
The Watchdog function monitors the WDI input to check
that WDI pulses arrive more frequently than the
programmed minimum rate. Monitoring commences after
two sequential time periods (the POR and BOOT Delays)
which start when the SMPS output reaches regulation. After
these initial time periods, time between WDI falling edges
exceeding the Watchdog Delay indicates abnormal
microcontroller activity, and the NCV8881 responds by
pulling the open drain RESB output low. A single external
resistor from the RDLY pin to ground programs the POR,
BOOT and Watchdog Delays.
When enabled and upon the SMPS output reaching
regulation, the NCV8881 enters the POR Delay period
t
POR
, during which the RESB pin is held low. When the
POR Delay expires, the NCV8881 enters the BOOT Delay
period t
BD
during which the RESB output is allowed to be
pulled up by the external resistance. When the BOOT Delay
expires, the Watchdog circuit begins monitoring the WDI
pin for a falling edge (from a microprocessor or other signal
source). If a falling edge arrives before the Watchdog Delay
period t
WD
expires, RESB remains high and a new
Watchdog Delay period is initiated. Otherwise the
NCV8881 enters another POR Delay period and the RESB
pin is pulled low, while the SMPS and LDO outputs continue
to regulate. If EN is low when the Watchdog Delay expires
(no falling edge has occurred at the WDI input), RESB is
pulled low and the NCV8881 shuts off all power outputs
(SMPS and LDOs) and minimizes supply current.
In order to ensure that WDI pulses keep RESB from being
pulled low, they must never occur further apart than the
minimum specified t
WD
. However, RESB is not guaranteed
to be pulled low unless pulses occur further apart than the
maximum specified t
WD
.
Removal of other conditions that cause RESB to go low
(V
IN
> V
OVSTP
, temperature > T
TSD
, and SMPS output
voltage low) also initiate POR and BOOT Delays prior to
resumption of WDI monitoring.
Figures 52 through 57 illustrate the action of RESB and
the POR, BOOT, and Watchdog Delays during startup and
shutdown.
The Watchdog Delay is internally limited to a maximum
value proportional to the switching period in case the
resistance at the RDLY pin becomes excessively high, such
as would occur if the path from the RDLY pin through the
RDLY resistance becomes an open circuit.
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