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參數資料
| 型號： | ORLI10G-1BM416I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| 封裝： | PLASTIC, MULTILAYER, BGA-416 |
| 文件頁數： | 1/74頁 |
| 文件大?。?/td> | 1411K |
| 代理商： | ORLI10G-1BM416I |
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Preliminary Data Sheet
March 2001
ORCA ORLI10G Field-Programmable System Chip
10 Gbits/s Transmit and Receive Line Interface
Introduction
Agere Systems Inc has developed a new ORCA Series
4 based FPSC, which combines a high-speed line inter-
face with a flexible FPGA logic core. Built on the Series
4 reconfigurable embedded system-on-chips (SoC)
architecture, the ORLI10G consists of an OIF standard
(OIF 99.102.5) compliant XSBI 10 Gbits/s transmit and
10 Gbits/s receive line interface. Both transmit and
receive interfaces consist of 16-bit LVDS data up to
667 Mbits/s, integrated transmit and receive program-
mable PLLs for data rate conversions between the line-
side and system-side data rates, and a programmable
logic interface at the system end for use with
SONET/SDH, Ethernet, or OTN/digital wrapper with
strong FEC system device data standards. In addition to
the embedded functionality, the device will include up to
400k of usable FPGA gates. The line interface includes
logic to divide the data rate down to 167 MHz or less
(1/4 line rate) or 84 MHz or less (1/8 line rate) for trans-
fer to the FPGA logic. The ORLI10G is designed to con-
nect directly to Lucent’s 10 Gbits/s TTRN0110G MUX
and TRCV0110G deMUX on the line side as well as
other industry-standard devices. The programmable
logic interface on the system side allows for direct con-
nection to a 10 Gbits/s Ethernet MAC, a 10 Gbits/s
SONET/SDH framer/data engine, or a 10 Gbits/s digital
wrapper/FEC framer/data engine.
For 10 Gbits/s Ethernet, the ORLI10G supports the
physical coding sublayer (PCS), interfaces to the physi-
cal media attachment (PMA), and connects to the sys-
tem interface (host or switch) for the proposed IEEE*
802.3ae 10 Gbits/s serial LAN PHY.
The ORLI10G FPSC is a high-speed programmable
device for 10 Gbits/s data solutions. It can be used as
the interface between the line interface and the system
interface in a variety of emerging networks, including
10 Gbits/s SONET/SDH (OC-192/STM-48), 10 Gbits/s
optical transport networks (OTN) using digital wrapper
and strong FEC, or 10 Gbits/s Ethernet. Other functions
include use in Quad OC-48/STM-16 SONET/SDH sys-
tems, interfaces between Quad OC-48/STM-16 and
OC-192/STM-64 components, and use as a generic
data transfer mechanism between two devices at
10 Gbits/s rates. Data is received at the line interface
and then sent to either a 4-bit or 8-bit serial-to-parallel
converter. On the transmit interface, either a 4-bit or
8-bit parallel-to-serial converter is used. Thus, the data
rate at the internal FPGA interface is either 1/4 or 1/8
the line rate.
The programmable PLLs on the ORLI10G provide for
great flexibility in handling clock rate conversion due to
differing amounts of overhead bits in various system
data standards. For example, when used as a
10 Gbits/s Ethernet interface, the ORLI10G will auto-
matically divide the line frequency of 645 MHz by
4 x 66/64 (receive side) to synchronize with the system
frequency of 156 MHz. When the ORLI10G is used as
an interface to a 10 Gbits/s digital wrapper/FEC framer/
data engine, these same PLLs can divide the strong
FEC standard line frequency of 667 MHz by 4 x 15/14
(receive side) to provide the 156 MHz system clock fre-
quency. The ORLI10G can also divide down the STS-
192/STM-64 SONET/SDH data line rate of 622 MHz by
4 to synchronize with a 155 MHz system clock. The
ORLI10G can also be configured to provide a 78 MHz
system data rate.
* IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA ORLI10G—Available FPGA Logic
The embedded core and interface are not included in the above gate counts. The usable gate counts range from a logic-only gate count
to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIO
groups are counted as 16 gates (three FFs, fast-capture latch, output logic, CLK, and I/O buffers). PFUs used as RAM are counted at four
gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU. Embedded block RAM (EBR) is counted as
four gates per bit plus each block has an additional 25k gates. 7k gates are used for each PLL and 50k gates for the embedded system
bus and microprocessor interface logic. Both the EBR and PLLs are conservatively utilized in the gate count calculations.
Device
PFU
Rows
PFU
Columns
Total
PFUs
User I/Os
LUTs
EBR
Blocks
EBR Bits
(k)
Usable
Gates (k)
ORLI10G
36
1296
432
10368
12
111
380—800
相關PDF資料 |
PDF描述 |
|---|---|
| ORLI10G-1BMN416I | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-1BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-1BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
| ORLI10G-2BM416 | FPGA, 1296 CLBS, 380000 GATES, PBGA416 |
| ORLI10G-2BM680 | FPGA, 1296 CLBS, 380000 GATES, PBGA680 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ORLI10G-1BM680C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BM680I | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-1BMN680I | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORLI10G-2BM680C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 316 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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