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參數資料
| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現場可編程系統芯片（促進文化基金）四通道x 622 Mbits /秒背板收發器 |
| 文件頁數： | 1/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORT4622 |
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Preliminary Data Sheet
March 2000
ORCA
ORT4622 Field-Programmable System Chip (FPSC)
Four-Channel x 622 Mbits/s Backplane Transceiver
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of FPGA-based design implemen-
tation, coupled with high-speed serial backplane data
transfer. The 622 Mbits/s backplane transceiver
offers a clockless, high-speed interface for interde-
vice communication on a board or across a back-
plane. The built-in clock recovery of the ORT4622
allows for higher system performance, easier-to-
design clock domains in a multiboard system, and
fewer signals on the backplane. Network designers
will benefit from the backplane transceiver as a net-
work termination device. The backplane transceiver
offers SONET scrambling/descrambling of data and
streamlined SONET framing, pointer moving, and
transport overhead handling, plus the programmable
logic to terminate the network into proprietary sys-
tems. For non-SONET applications, all SONET func-
tionality is hidden from the user and no prior
networking knowledge is required.
Embedded Core Features
I
Implemented in an ORCA Series 3 FPGA array.
I
Allows wide range of applications for SONET net-
work termination application as well as generic data
moving for high-speed backplane data transfer.
I
No knowledge of SONET/SDH needed in generic
applications. Simply supply data, 78 MHz clock, and
a frame pulse.
I
High-speed interface (HSI) function for clock/data
recovery serial backplane data transfer without
external clocks.
I
HSI function uses Lucent Technologies Microelec-
tronics Group’s proven 622 Mbits/s serial interface
core.
I
Four-channel HSI function provides 622 Mbits/s
serial interface per channel for a total chip band-
width of 2.5 Gbits/s (full duplex).
I
LVDS I/Os compliant with EIA*-644, support hot
insertion.
I
8:1 data multiplexing/demultiplexing for 77.76 MHz
byte-wide data processing in FPGA logic.
I
On-chip phase-lock loop (PLL) clock meets B jitter
tolerance specification of ITU-T Recommendation
G.958 (0.6
UI
P-P
at 250 kHz).
I
Powerdown option of HSI receiver on a per-
channel basis.
I
Highly efficient implementation with only 3% over-
head vs. 25% for 8B10B coding.
I
In-Band management and configuration.
I
Streamlined pointer processor (pointer mover) for
8 kHz frame alignment to system clocks.
I
Built-in boundry scan (IEEE
1149.1 JTAG).
I
FIFOs align incoming data across all four channels
for STS-48 (2.5 Gbits/s) operation (in quad STS-12
format).
I
1 + 1 protection supports STS-12/STS-48 redun-
dancy by either software or hardware control for
protection switching applications.
* EIA is a registered trademark of Electronic Industries Associa-
tion.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCAORT4622—Available FPGA Logic
The embedded core and interface are not included in the above gate counts. The usable gate count range from a logic-only gate count to
a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only gate count includes each PFU/SLIC (counted as
108 gates per PFU/SLIC), including 12 gates pre-LUT/FF pair (eight per PFU), and 12 gates per SLC/FF pair (one per PFU). Each of the
four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic, CLK drivers, and I/O buffers). PFUs used as RAM are
counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or 512 gates) per PFU.
Device
Usable
System
Gates
60K—120K
Number of
LUTs
Number of
Registers
Max User
RAM
Max User
I/Os
Array Size
Number of
PFUs
ORT4622
4032
5304
64K
259
18 x 28
504
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