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參數資料
| 型號： | P2065A-08ST |
| 英文描述： | MCU CMOS 20LD 20NHz 4K FLASH, -40C to +85C, 20-SSOP 208mil, T/R |
| 中文描述： | 外圍芯片 |
| 文件頁數： | 2/7頁 |
| 文件大小： | 94K |
| 代理商： | P2065A-08ST |
Final Product Specification
P2065
Jan., 2001
Revision D
3160 De La Cruz Blvd., Suite 200 Santa Clara CA 95054 Tel (408)
748-6988
Fax (408)
748-000
9
Figure 2 – P2065 Block Diagram
Modulation
Phase
Detector
Frequency
Divider
Feedback
Divider
Loop
Filter
VCO
Output
Divider
PLL
SR0 SR1 MRA SSON
CLKIN
VDD
VSS
ModOUT
P2065 Block Diagram
Table 1 – Modulation Selection
MRA
SR1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
**NOTE: THESE SETTINGS ARE NOT RECOMMENDED FOR 5.0V OPERATION
Pin Description
PIN #
Name
Type
Description
1
CLKIN
I
External reference frequency input.
Connect to externally generated
reference signal. Select appropriate part for the intended input frequency
(see Table 1).
2
MRA
I
Digital logic input used to select modulation rate (see Table 3). This pin has
a 100K Ohm internal pull-up resistor.
3
SR1
I
Digital logic input used to select Spreading Range (see Table 2). This pin
has a 100K Ohm internal pull-up resistor.
4
VSS
P
Ground Connection. Connect to system ground.
5
SSON
I
Digital logic input used to enable Spread Spectrum function (Active Low).
Spread Spectrum function enable when low. This pin has a 100K Ohm
internal pull-low resistor.
6
ModOUT
O
Spread Spectrum Clock Output.
7
SR0
I
Digital logic input used to select Spreading Range (see Table 1). This pin
has a 100K Ohm internal pull-up resistor.
8
VDD
P
Connect to +3.3V or +5.0V
SR0
0
1
0
1
0
1
0
1
Spreading Range
+/- 0.3%
+/- 0.6%
+/- 0.4%
+/- 0.8%
+/- 0.5%
+/- 1.00%
RESERVED
RESERVED
Modulation Rate
(Fin/40) * 34.72 KHz **
(Fin/40) * 34.72 KHz **
(Fin/40) * 34.72 KHz **
(Fin/40) * 34.72 KHz
(Fin/40) * 20.83 KHz
(Fin/40) * 20.83 KHz
RESERVED
RESERVED
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