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參數資料
| 型號： | P4C1041-20TI |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 256K x 16 (4 MEG) STATIC CMOS RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 20 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 453K |
| 代理商： | P4C1041-20TI |
1
Document #
SRAM133
REV OR
Revised January 2007
P4C1041
HIGH SPEED 256K x 16 (4 MEG)
STATIC CMOS RAM
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
Low Power
Single 5.0V ± 10% Power Supply
2.0V Data Retention
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
FEATURES
DESCRIPTION
The P4C1041 is a 262,144 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 5.0V ± 10% tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P4C1041
is a member of a family of PACE RAM products offer-
ing fast access times.
The P4C1041 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
to A
. Reading is
accomplished by device selection (
CE
and output en-
abling (
OE
) while write enable (
WE
) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
Package options for the P4C1041 include 44-pin SOJ
and TSOP packages.
Easy Memory Expansion Using
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
CE
and
OE
SOJ
TSOP II
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