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參數資料
| 型號： | P4C187L-45JMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS |
| 中文描述： | 64K X 1 STANDARD SRAM, 45 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-24 |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 323K |
| 代理商： | P4C187L-45JMB |
1
Document #
SRAM111
REV B
Revised April 2007
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
– 743 mW Active -10
– 660/770 mW Active for -12/15
– 550/660 mW Active for -20/25 35
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C187
– 5.5 mW Standby (CMOS Input) P4C187L (Military)
Single 5V±10% Power Supply
P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P3, D3, C3)
LCC Pin configurations at end of datasheet.
Data Retention with 2.0V Supply (P4C187L
Military)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTION
The P4C187/P4C187L are 65, 536-bit ultra high speed
static RAMs organized as 64K x 1. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. The RAMs operate from a single 5V ± 10%
tolerance power supply. Data ntegrity s maintained for sup-
ply voltages down to 2.0V, typically drawing 10μA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
SOJ (J4)
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