- 您現在的位置：買賣IC網 > PDF目錄382369 > P87LPC761 (NXP Semiconductors N.V.) Low power, low price, low pin count (16 pin) microcontroller with 2 kbyte OTP PDF資料下載
參數資料
| 型號： | P87LPC761 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low power, low price, low pin count (16 pin) microcontroller with 2 kbyte OTP |
| 中文描述： | 低功耗，低價格，低引腳數（16針）2字節檢察官辦公室微控制器 |
| 文件頁數： | 39/58頁 |
| 文件大小： | 299K |
| 代理商： | P87LPC761 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
Philips Semiconductors
Preliminary data
P87LPC761
Low power, low price, low pin count (16 pin)
microcontroller with 2 kbyte OTP
2002 Mar 07
36
More About UART Mode 0
Serial data enters and exits through RxD. TxD outputs the shift
clock. 8 bits are transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/6 the CPU clock frequency. Figure 32 shows
a simplified functional diagram of the serial port in Mode 0, and
associated timing.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal at S6P2 also loads a
1 into the 9th position of the transmit shift register and tells the TX
Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “write to SBUF”
and activation of SEND.
SEND enables the output of the shift register to the alternate output
function line of P1.1 and also enable SHIFT CLOCK to the alternate
output function line of P1.0. SHIFT CLOCK is low during S3, S4, and
S5 of every machine cycle, and high during S6, S1, and S2. At
S6P2 of every machine cycle in which SEND is active, the contents
of the transmit shift are shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When
the MSB of the data byte is at the output position of the shift register,
then the 1 that was initially loaded into the 9th position, is just to the
left of the MSB, and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift and then
deactivate SEND and set T1. Both of these actions occur at S1P1 of
the 10th machine cycle after “write to SBUF.” Reception is initiated by
the condition REN = 1 and R1 = 0. At S6P2 of the next machine
cycle, the RX Control unit writes the bits 11111110 t o the receive shift
register, and in the next clock phase activates RECEIVE.
RECEIVE enable SHIFT CLOCK to the alternate output function line
of P1.0. SHIFT CLOCK makes transitions at S3P1 and S6P1 of every
machine cycle. At S6P2 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left
one position. The value that comes in from the right is the value that
was sampled at the P1.1 pin at S5P2 of the same machine cycle.
As data bits come in from the right, 1s shift out to the left. When the 0
that was initially loaded into the rightmost position arrives at the
leftmost position in the shift register, it flags the RX Control block to do
one last shift and load SBUF. At S1P1 of the 10th machine cycle after
the write to SCON that cleared RI, RECEIVE is cleared as RI is set.
More About UART Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a
start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the
stop bit goes into RB8 in SCON. In the P87LPC761 the baud rate is
determined by the Timer 1 overflow rate. Figure 33 shows a
simplified functional diagram of the serial port in Mode 1, and
associated timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a
destination register. The “write to SBUF” signal also loads a 1 into
the 9th bit position of the transmit shift register and flags the TX
Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover
in the divide-by-16 counter. (Thus, the bit times are synchronized to
the divide-by-16 counter, not to the “write to SBUF” signal.)
The transmission begins with activation of SEND which puts the
start bit at TxD. One bit time later, DATA is activated, which enables
the output bit of the transmit shift register to TxD. The first shift pulse
occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left.
When the MSB of the data byte is at the output position of the shift
register, then the 1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the left of that contain
zeros. This condition flags the TX Control unit to do one last shift
and then deactivate SEND and set TI. This occurs at the 10th
divide-by-16 rollover after “write to SBUF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this
purpose RxD is sampled at a rate of 16 times whatever baud rate
has been established. When a transition is detected, the
divide-by-16 counter is immediately reset, and 1FFH is written into
the input shift register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the
7th, 8th, and 9th counter states of each bit time, the bit detector
samples the value of RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for noise rejection.
If the value accepted during the first bit time is not 0, the receive
circuits are reset and the unit goes back to looking for another 1-to-0
transition. This is to provide rejection of false start bits. If the start bit
proves valid, it is shifted into the input shift register, and reception of
the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left. When the
start bit arrives at the leftmost position in the shift register (which in
mode 1 is a 9-bit register), it flags the RX Control block to do one
last shift, load SBUF and RB8, and set RI. The signal to load SBUF
and RB8, and to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated.: 1.
R1 = 0, and 2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions is not met, the received frame is
irretrievably lost. If both conditions are met, the stop bit goes into
RB8, the 8 data bits go into SBUF, and RI is activated. At this time,
whether the above conditions are met or not, the unit goes back to
looking for a 1-to-0 transition in RxD.
相關PDF資料 |
PDF描述 |
|---|---|
| P87LPC762 | Low power, low price, low pin count 20 pin microcontroller with 2 kbyte OTP |
| P87LPC768 | Low Power, Low System Cost 80C51 MCU with ADC and PWM |
| P87LPC768BN | Low Power, Low System Cost 80C51 MCU with ADC and PWM |
| P88-3004 | TONER VACUUM STD 220/240V |
| P88-3005 | TONER FILTER STD 0.3 MICRON |
相關代理商/技術參數 |
參數描述 |
|---|---|
| P87LPC761BDH | 功能描述:8位微控制器 -MCU 2K/128 OTP 2.7-6V COMM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC761BDH,112 | 功能描述:8位微控制器 -MCU 2K/128 OTP 2.7-6V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC761BN | 功能描述:8位微控制器 -MCU 2K/128 OTP 2.7-6V COMM DIP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC761BN,112 | 功能描述:8位微控制器 -MCU 2K/128 OTP 2.7-6V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| P87LPC762 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low power, low price, low pin count 20 pin microcontroller with 2 kbyte OTP |
發布緊急采購，3分鐘左右您將得到回復。