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參數(shù)資料
| 型號： | PALC22V10B |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | PAL |
| 英文描述： | Reprogrammable CMOS PAL Device |
| 中文描述： | 可再編程的CMOS PAL制式設(shè)備 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大小： | 78K |
| 代理商： | PALC22V10B |
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ALL NEW DESIGNS
Reprogrammable CMOS PAL
Device
PALC22V10B
This is an abbreviated data sheet. Contact a Cypress
representative for complete specifications.
Cypress Semiconductor Corporation
Document #: 38-03018 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised April 22, 2004
Features
Advanced second generation PAL architecture
Low power
— 90 mA max. standard
— 100 mA max. military
CMOS EPROM technology for reprogrammability
Variable product terms
— 2 x (8 through 16) product terms
User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combina-
torial operation
— 15 ns commercial and industrial
10 ns t
CO
10 ns t
S
15 ns t
PD
50 MHz
— 15 ns and “20 ns” military
10/15 ns t
CO
10/17 ns t
S
15/20 ns t
PD
50/31 MHz
Up to 22 input terms and 10 outputs
Enhanced test features
— Phantom array
— Top test
— Bottom test
— Preload
High reliability
— Proven EPROM technology
— 100% programming and functional testing
Windowed DIP, windowed LCC, DIP, LCC, PLCC
available
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the “Programmable Macrocell.”
The PALC22V10B is executed in a 24-pin 300-mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic
leadless chip carrier, a 28-lead square plastic leaded chip
carrier, and provides up to 22 inputs and 10 outputs. When the
windowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually
LogicBlockDiagram(PDIP/CDIP)
Macrocell
8
10
12
14
16
16
14
12
10
8
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
Preset
PROGRAMMABLE
ANDARRAY
(132X44)
I
I
I
I
I
I
I
I
I
I
CP/I
VSS
I
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
相關(guān)PDF資料 |
PDF描述 |
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| PALC22V10D | FLASG ERASABLE REPROGRAMMABLE CMOS PAL DEVICE |
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| PALCE22V10 | Flash Erasable,Reprogrammable CMOS PAL Device(可擦除閃速，CMOS可重編程PAL器件) |
| PALLV16V8-10JC | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
| PALLV16V8-10PC | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PALC22V10B-15HC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PALC22V10B15HMB | 制造商:CYPRESS 功能描述:* |
| PALC22V10B15JC | 制造商:CYPRESS 功能描述:New |
| PALC22V10B-15JC | 制造商:Cypress Semiconductor 功能描述:SPLD PAL |
| PALC22V10B-15JI | 制造商:Cypress Semiconductor 功能描述:SPLD PAL? Family 10 Macro Cells 50MHz 5V 28-Pin PLCC |
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