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參數資料
| 型號： | PCA8581CP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DRAM |
| 英文描述： | 128 x 8-bit EEPROM with I2C-bus interface |
| 中文描述： | 128 X 8 EEPROM 3V, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001AN, SOT-97-1, DIP-8 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 107K |
| 代理商： | PCA8581CP |
1997 Apr 02
6
Philips Semiconductors
Product specification
128
×
8-bit EEPROM with I
2
C-bus interface
PCA8581; PCA8581C
7.3
System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
Fig.5 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
7.4
Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
Fig.6 Acknowledgement on the I
2
C-bus.
handbook, full pagewidth
MBA606 - 1
START
condition
S
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
clock pulse for
acknowledgement
1
2
8
9
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| PCA8581T | 128 x 8-bit EEPROM with I2C-bus interface |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCA8581CT | 制造商:NXP Semiconductors 功能描述: |
| PCA8581CT/6,112 | 功能描述:電可擦除可編程只讀存儲器 128X8 電可擦除可編程只讀存儲器 I2C-BUS SO-8 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| PCA8581CT/6,118 | 功能描述:電可擦除可編程只讀存儲器 128X8 電可擦除可編程只讀存儲器 I2C-BUS SO-8 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數據保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| PCA8581CTD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
| PCA8581P | 制造商:NXP Semiconductors 功能描述:128 X 8 EEPROM 5V, PDIP8 |
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