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參數資料
| 型號： | PCA8591P |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit A/D and D/A converter |
| 中文描述： | 8位A / D和D / A轉換器 |
| 文件頁數： | 6/28頁 |
| 文件大小： | 221K |
| 代理商： | PCA8591P |
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1998 Jul 02
6
Philips Semiconductors
Product specification
8-bit A/D and D/A converter
PCF8591
7
FUNCTIONAL DESCRIPTION
7.1
Addressing
Each PCF8591 device in an I
2
C-bus system is activated by
sending a valid address to the device. The address
consists of a fixed part and a programmable part.
The programmable part must be set according to the
address pins A0, A1 and A2. The address always has to
be sent as the first byte after the start condition in the
I
2
C-bus protocol. The last bit of the address byte is the
read/write-bit which sets the direction of the following data
transfer (see Figs 3, 15 and 16).
Fig.3 Address byte.
7.2
Control byte
The second byte sent to a PCF8591 device will be stored
in its control register and is required to control the device
function.
The upper nibble of the control register is used for enabling
the analog output, and for programming the analog inputs
as single-ended or differential inputs. The lower nibble
selects one of the analog input channels defined by the
upper nibble (see Fig.4). If the auto-increment flag is set
the channel number is incremented automatically after
each A/D conversion.
If the auto-increment mode is desired in applications
where the internal oscillator is used, the analog output
enable flag in the control byte (bit 6) should be set. This
allows the internal oscillator to run continuously, thereby
preventing conversion errors resulting from oscillator
start-up delay. The analog output enable flag may be reset
at other times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the
highest available channel number being allocated.
Therefore, if the auto-increment flag is set, the next
selected channel will be always channel 0. The most
significant bits of both nibbles are reserved for future
functions and have to be set to 0. After a Power-on reset
condition all bits of the control register are reset to 0.
The D/A converter and the oscillator are disabled for power
saving. The analog output is switched to a high-impedance
state.
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