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參數資料
| 型號： | PCA9554N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit I2C and SMBus I/O port with interrupt |
| 中文描述： | 8 I/O, PIA-GENERAL PURPOSE, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MO-001, SOT-38-1, DIP-16 |
| 文件頁數： | 12/20頁 |
| 文件大小： | 183K |
| 代理商： | PCA9554N |
Philips Semiconductors
Product data sheet
PCA9554/PCA9554A
8-bit I
2
C and SMBus I/O port with interrupt
2004 Sep 30
12
SDA
SCL
SU01469
t
HD;STA
t
F
S
t
LOW
t
R
t
HD;DAT
t
SU;DAT
t
HIGH
t
F
t
SU;STA
S
R
t
HD;STA
t
SP
t
SU;STD
P
t
R
t
BUF
S
Figure 12. Definition of timing
AC SPECIFICATIONS
SYMBOL
PARAMETER
STANDARD MODE
I
2
C-BUS
MIN
0
FAST MODE
I
2
C-BUS
MIN
0
UNITS
MAX
100
MAX
400
f
SCL
t
BUF
t
HD;STA
t
SU;STA
t
SU;STO
t
HD;DAT
t
VD;ACK
t
VD;DAT
t
SU;DAT
t
LOW
t
HIGH
t
F
t
R
t
SP
Operating frequency
kHz
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
Bus free time between STOP and START conditions
4.7
—
1.3
—
Hold time after (repeated) START condition
4.0
—
0.6
—
Repeated START condition setup time
4.7
—
0.6
—
Setup time for STOP condition
4.0
—
0.6
—
Data in hold time
Valid time for ACK condition
2
Data out valid time
3
0
—
0
—
0.3
3.45
0.1
0.9
300
—
50
—
Data setup time
250
—
100
—
ns
μ
s
μ
s
ns
Clock LOW period
4.7
—
1.3
—
Clock HIGH period
4.0
—
0.6
—
Clock/Data fall time
—
300
20 + 0.1 C
b1
20 + 0.1 C
b1
—
300
Clock/Data rise time
—
1000
300
ns
Pulse width of spikes that must be suppressed by the
input filters
—
50
50
ns
Port Timing
t
PV
t
PS
t
PH
Output data valid
—
200
—
200
ns
Input data setup time
100
—
100
—
ns
μ
s
Input data hold time
1
—
1
—
Interrupt Timing
t
IV
t
IR
Interrupt valid
—
4
—
4
μ
s
μ
s
Interrupt reset
—
4
—
4
NOTES:
1. C
b
= total capacitance of one bus line in pF.
2. t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
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