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參數資料
| 型號： | PCB2032V |
| 元件分類： | DRAM |
| 英文描述： | EEPROM |
| 中文描述： | EEPROM的 |
| 文件頁數： | 10/18頁 |
| 文件大?。?/td> | 220K |
| 代理商： | PCB2032V |
1997 Feb 03
10
Philips Semiconductors
Product Specification
Memory card IC
PCB2032
5.4
Description of Commands
5.4.1
R
EAD
M
AIN
M
EMORY
The READ MAIN MEMORY command reads out the
content of the Main Memory starting at the given byte
address up to the end of the memory (address 255). The
read access to the Main Memory is always possible.
5.4.2
R
EAD
P
ROTECTION
M
EMORY
The READ PROTECTION MEMORY command reads out
the Protection Memory starting at address 0x00 up to the
end of the memory (address 0x03). The read access to the
Protection Memory is always possible.
5.4.3
U
PDATE
/W
RITE
C
OMMANDS
The EEPROM programming is defined as:
Erase:
change EEPROM byte from 0xXX to 0xFF
Write:
change EEPROM bits from HIGH to LOW (no
changes from LOW to HIGH)
All other data changes require a complete Erase- and
Write-cycle.
If the data byte transmitted equals the current content of
the addressed EEPROM byte, neither the Erase- nor the
Write-cycle will be executed.
The Erase-cycle as well as the Write-cycle takes 2.5 ms
each.
Before any data can be programmed at least one of the
read commands or Answer-to-Reset must be given.
5.4.4
U
PDATE
M
AIN
M
EMORY
The UPDATE MAIN MEMORY command programs the
EEPROM cell addressed by ‘byte Address’ with the Data
byte transmitted.
The write attempt fails, if the addressed byte has been
protected by the appropriate Protection bit.
5.4.5
W
RITE
P
ROTECTION
M
EMORY
The WRITE PROTECTION MEMORY command
programs the EEPROM protection bit addressed by ‘byte
Address’, only if the Data byte transmitted equals the data
content of the EEPROM byte to be protected. If the
transmitted data byte does not match, the Protection bit
will not be set.
If the transmitted address is greater than 0x1F, the
command is ignored.
6
RESET MODES
6.1
Reset
If RST is set to HIGH for at least 5
μ
s and if the IFD keeps
CLK in low state during the reset pulse, the IC aborts any
operation, sets the I/O line to HIGH and is then ready for
further operations.
6.2
Answer-To-Reset
The Answer-to-reset is initiated according to ISO standard
7816-3. The four data bytes of the ATR are serially output
to I/O with LSB first when 32 clock pulses are applied to
CLK. The I/O is set to HIGH after an additional clock pulse
(see Fig.3 and Chapter 5).
6.3
Power on Reset
After applying the operating voltage VCC, the I/O goes to
HIGH. Before any data can be programmed at least one of
the read commands or Answer-to-Reset must be given.
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