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參數資料
| 型號： | PCD3316T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網絡 |
| 英文描述： | Caller-ID on Call Waiting CIDCW receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | 7.50 MM, PLASTIC, SOT-162-1, SO-16 |
| 文件頁數： | 16/30頁 |
| 文件大小： | 534K |
| 代理商： | PCD3316T |
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Philips Semiconductors
PCD3316
CIDCW receiver
Product specification
11 March 1999
16 of 30
9397 750 04824
Philips Electronics N.V. 1999. All rights reserved.
CIDSTA.7
POL1
CIDSTA.6
POL0
CIDSTA.5
LOW-BAT Indication LOW-BAT Indication = 0: voltage on input LOWBAT > V
ref
;
LOW-BAT Indication = 1: voltage on input LOWBAT < V
ref
CIDSTA.4
FSK-BOM Indication FSK-BOM Indication = 0: begin of mark period not yet detected;
FSK-BOM Indication = 1: begin of mark period detected
CIDSTA.3
FSK-OVR Error
FSK-OVR Error = 0: no FSK overrun error;
FSK-OVR Error = 1: FSK overrun error, data byte(s) lost
CIDSTA.2
FSK-FRM Error
FSK-FRM Error = 0: no FSK frame error;
FSK-FRM Error = 1: FSK frame error, stop bit was wrong
CIDSTA.1 and
CIDSTA.0
7.13.2
FSK data register (CDFSK)
7.13.3
Status register (CIDSTA)
7.13.4
Ringer period register (CIDRNG)
Table 7:
Address: 01H; read only.
7
D7
Interrupt register
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
Table 8:
Bit
CDFSK.7 to
CDFSK.0
Description of CDFSK bits
Symbol
D7 to D0
Description
If an FSK interrupt has occurred and no FSK error is detected, the FSK data register
contains valid data.
Table 9:
Address: 02H; read only.
7
6
POL1
POL0
Status register
5
4
3
2
1
0
LOW-BAT Indication
FSK-BOM Indication
FSK-OVR Error
FSK-FRM Error
Table 10: Description of CIDSTA bits
Bit
Symbol
Description
POL1 = 0: voltage on input POL1 < V
ref
; POL1 = 1: voltage on input POL1 > V
ref
POL0 = 0: voltage on input POL0 > V
ref
; POL0 = 1: voltage on input POL0 < V
ref
reserved bits
Table 11: Register format
Address: 03H; read only.
7
D7
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
Table 12:
Bit
CIDRNG.7 to
CIDRNG.0
Description of CIDRNG bits
Symbol
D7 to D0
Description
The value held in this byte denotes the time between two positive edges of the POL1
comparator output (between two positive edges of POL1 one positive edge of POL0
must have been detected).
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