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參數資料
| 型號： | PCD4440T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Analog voice scrambler/descrambler |
| 中文描述： | TELECOM, CORDLESS, SCRAMBLER/DESCRAMBLER, PDSO8 |
| 封裝： | 7.50 MM, PLASTIC, SOT-176-1, SOP-8 |
| 文件頁數： | 11/20頁 |
| 文件大小： | 105K |
| 代理商： | PCD4440T |
1996 Dec 20
11
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
8.5
Timing specifications
The PCD4440T accepts data input from a microcontroller and operates as a ‘slave receiver’ via the I
2
C-bus. It supports
the ‘standard’ mode of the I
2
C-bus, but not the ‘fast’ mode detailed in “The I
2
C-bus and how to use it” document order
no. 9398 393 40011. The timing requirement are as follows:
Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig. 10, where the two
signal levels are LOW = V
IL
and HIGH = V
IH
, see Chapter 12. The time symbols are explained in Table 2. Figure 11
shows a complete data transfer.
Fig.10 Standard mode timing.
handbook, full pagewidth
MBC764
tBUF
tf
tHIGH
tSU;DAT
tSU;STO
tHD;DAT
tSU;STA
tr
tLOW
tHD;STA
SDA
SCL
SDA
Fig.11 Complete data transfer in standard mode.
handbook, full pagewidth
MBC765
9
8
1 - 7
9
8
1 - 7
9
8
1 - 7
STOP
ACK
ADDRESS
R/W
START
CONDITION
ACK
DATA
START
CONDITION
ACK
ADDRESS
R/W
SCL
Clock LOW minimum = 4.7
μ
s; clock HIGH minimum = 4
μ
s.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
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