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參數資料
| 型號： | PCD5093H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網絡 |
| 英文描述： | DECT baseband controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 文件頁數： | 6/16頁 |
| 文件大小： | 85K |
| 代理商： | PCD5093H |
1997 Jul 21
6
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5093
5.2
Pin description
Table 1
QFP100 package
SYMBOL
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
PIN DESCRIPTION
ANT_SW1
ANT_SW0
CLK100
T_ENABLE
T_PWR_RMP
T_DATA
T_GMSK
VCO_BND_SW
SYNTH_LOCK
S_ENABLE
S_DATA
S_CLK
S_PWR
REF_CLK
V
SS1
V
DD_RF
V
DD3V_1
SLICE_CTR
R_PWR
R_DATAP
R_DATAM
R_ENABLE
RSSI_AN
VANLI
VBAT
CLK3
DCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
O
O
O
O
O
O
O
O
I
O
O
O
O
O
O
O
I
I
O
I
I
I
O
I/O
H
H
H
H
L
off
L
L
L
L
L
H
ISP2DRF3
ISP2DRF3
ISP2DPES
ISP2DRF3
ISP2DRF3
ISF2DRF3
ANAIOD1
ISP2DRF3
DIPP0RF3
ISP2DRF3
ISP2DRF3
ISP2DRF3
ISP2DRF3
ISP4DRF3
supply
supply
supply
ISP2DRF3
ISP2DRF3
ANAIOD2
ANAIOD2
ISP2DRF3
ANAIOD1
ANAIOD1
ANAIOD1
ISP2DPES
ISF2DPES
ISF2UPES
DIPP0PES
ISF2DPES
ISF2UPES
ISI8DPES
ANAIOD1
ANAIOD1
ANAIOD1
antenna switch 1 output
antenna switch 0 output
100 Hz signal related to DECT frame timing output
enable transmitter output
switch transmitter power output
unmodulated transmitter data output
GMSK modulated transmitter data output
VCO band switch output
synthesizer lock input
synthesizer enable output
serial synthesizer data output
clock for serial synthesizer interface output
switch synthesizer power output
13.824 MHz reference clock for synthesizer output
negative supply voltage 1
positive supply voltage for RF interface level shifters
positive supply voltage 1 (+3 V)
switch slicer time constant output
switch receiver power output
positive input for receiver data
negative input for receiver data
enable receiver output
analog input for RSSI measurement
analog input to ADC
analog input for battery voltage measurement
3.456 MHz clock output for external ADPCM codec
ADPCM output or IOM data clock input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
ADPCM or IOM data input
8 kHz framing input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
ADPCM or IOM data output
crystal oscillator output
crystal oscillator input
analog output from D/A converter
running
L
H
H
L
input
DI
FS1
28
29
I
I/O
input
DO
XTAL2
XTAL1
VANLO
30
31
32
33
O
O
I
O
off
running
1.0 V
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| PCD5094 | DECT baseband controller |
| PCD5094H | DECT baseband controller |
| PCD5095 | DECT baseband controller |
| PCD5095H | DECT baseband controller |
| PCD5096 | Universal codec |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCD5094 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controller |
| PCD5094H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controller |
| PCD5095 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controller |
| PCD5095H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DECT baseband controller |
| PCD5096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:解碼芯片 |
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