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參數資料
| 型號： | PCM1712U |
| 英文描述： | DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 數字到模擬轉換器 |
| 文件頁數： | 12/16頁 |
| 文件大小： | 101K |
| 代理商： | PCM1712U |
12
PCM1712
DOUBLE-SPEED DUBBING
Double-speed dubbing is enabled when B7 is high. Since f
S
is set at 44.1kHz, the system clock in double-speed mode is
at 192fs.
MODE 2 CONTROLS
This mode is enabled when the first three bits on MD are 1,
0, 1. Mode 2 allows for the following functions:
SAMPLE RATE CLOCK POLARITY
B6 controls the polarity of the sample rate clock (LRCIN)
polarity. When B6 is low, data will be accepted on the left
channel when LRCIN is high, and on the right channel when
LRCIN is low. When B6 is high, data will be accepted on the
right channel when LRCIN is high, and on the left channel
when LRCIN is low.
INPUT FORMAT
Normal input mode for PCM1712 is MSB first, right justi-
fied. PCM1712 may also be operated with IIS input format.
When B7 is low, the input format is “normal”. When B7 is
high, the input format is “IIS”.
DEFAULT MODE
At initial power-on, default settings for PCM1712 are
44.1kHz f
S
, de-emphasis off, mute off, double speed off,
infinite zero detect on, 16-bit input LRCIN left channel high,
and normal input mode.
SYSTEM CLOCK
LR Polarity
Input Format
Controls Left/Right Channel Select
Normal/IIS (Philips format)
NORMAL/DOUBLE-SPEED DUBBING
For most CD playback applications operating at 384fs, the
system clock frequency must be 16.9344MHz, in both the
normal mode and double-speed dubbing mode. Table VIII
illustrates the relationship between fs and output clock
frequency in both modes.
SAMPLING FREQUENCY
SYSTEM CLOCK
FREQUENCY
32kHz
44.1kHz
48kHz
384fs
384fs
384fs
12.2880MHz
16.9344MHz
18.4320MHz
DSD
PARAMETER
H (Normal)
L (Double Speed)
XTI Input Clock Frequency
384fs
192fs
XTI Frequency
16.9344MHz
(f
S
= 44.1kHz)
384fs
16.9344MHz
(f
S
= 88.2kHz)
192fs
CLKO Output Clock Frequency
TABLE VIII. Relationship Between Normal/Double Speed
and fs.
FIGURE 7. External Crystal Oscillator.
Internal System Clock
XTI
XTO
CLKO (XTI)
C
1
C2
Crystal
C
1
, C
2
: 10pF ~ 22pF
EXTERNAL SYSTEM CLOCK
Figure 7 is a diagram showing the internal clock in conjunc-
tion with an external crystal oscillator.
Figure 8 is a diagram showing the internal clock with an
external clock source, instead of an oscillator. An external
system clock (input to XTI) must meet timing requirement
which is shown in Figure 6.
FIGURE 6. Timing Requirement for External System Clock
(XTi).
V
IH
> 0.64V
DD
V
IL
< 0.28V
DD
T
H
> 10ns
T
L
< 10ns
In case of system clock inputs to XTI from external, system clock should
be input with the following condition.
T
H
V
IH
V
IIL
T
L
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