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參數資料
| 型號： | PCM1720 |
| 英文描述： | Stereo Audio DIGITAL-TO-ANALOG CONVERTER MPEG2/AC-3 COMPATIBLE |
| 中文描述： | 立體聲音頻數字模擬轉換器MPEG2/AC-3兼容 |
| 文件頁數： | 9/13頁 |
| 文件大小： | 194K |
| 代理商： | PCM1720 |
PCM1720
9
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
res
res res
res
res A1
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEMMUTE
Register 2 is used to control soft mute, de-emphasis, opera-
tion enable, input resolution, and output format. Bit 0 is used
for soft mute: a “HIGH” level on bit 0 will cause the output
to be muted (this is ramped down in the digital domain, so
no “click” is audible). Bit 1 is used to control de-emphasis.
A “LOW” level on bit 1 disables de-emphasis, while a
“HIGH” level enables de-emphasis.
Bit 2, (OPE) is used for operational control. Table IV
illustrates the features controlled by OPE.
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Forced to BPZ
(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
TABLE IV. Output Enable (OPE) Function.
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65, 536 cycles of BCKIN,
the output will be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
IZD = 1
IZD = 0
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Forced to BPZ
(1)
Normal
Zero
(2)
Normal
TABLE V. Infinite Zero Detection (IZD) Function.
RSTB = “HIGH”
RSTB = “LOW”
SOFTWARE
MODE
INPUT
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Other
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ
(1)
Forced to BPZ
(1)
Enabled
Enabled
Disabled
Disabled
TABLE VI. Reset (RSTB) Function.
NOTE: (1)
∑
is disconnected from output amplifier. (2)
∑
is connected to
output amplifier.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1720 can be set up for input word resolu-
tions of 16, 20, or 24 bits:
Bit 4 (IW1)
Bit 3 (IW0)
Input Resolution
0
0
1
0
0
1
0
0
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1720 can be programmed for 16 different
states, as shown in Table VII.
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
REVERSE
STEREO
MONO
TABLE VII. Programmable Output Format.
REGISTER 3 (A1 = 1, A0 = 1)
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
res
res
res res res
A1
A0
IZD SF1 SF0
res
res
res ATC LRP I
2
S
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sam-
pling frequency and infinite zero detection.
Bits 0 (I
2
S) and 1 (LRP) are used to control the input data
format. A “LOW” on bit 0 sets the format to “Normal”
(MSB-first, right-justified Japanese format) and a “HIGH”
sets the format to I
2
S (Philips serial data protocol). Bit 1
(LRP) is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is “LOW”, left channel data is assumed
when LRCIN is in a “HIGH” phase and right channel data
is assumed when LRCIN is in a “LOW” phase. When bit
1 is “HIGH”, the polarity assumption is reversed.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is “HIGH”, the attenuation data loaded in program
Register 0 is used for both left and right channels. When
bit 2 is “LOW”, the attenuation data for each register is
applied separately to left and right channels.
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency:
SF1
SF0
Sampling Frequency
0
0
1
1
0
1
0
1
44.1kHz group
48kHz group
32kHz group
Reserved
22.05/44.1/88.2kHz
24/48/96kHz
16/32/64kHz
Not Defined
Bit 8 is used to control the infinite zero detection function
(IZD).
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| PCM1720E | 功能描述:音頻數/模轉換器 IC Ster DAC MPEG2/ AC-3 Compatible RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1720E/2K | 功能描述:音頻數/模轉換器 IC Ster DAC MPEG2/ AC-3 Compatible RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1720E/2KG4 | 功能描述:音頻數/模轉換器 IC Ster DAC MPEG2/ AC-3 Compatible RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1720EG4 | 功能描述:音頻數/模轉換器 IC Ster DAC MPEG2/ AC-3 Compatible RoHS:否 制造商:Texas Instruments 轉換器數量: 分辨率:16 bit 接口類型:I2S, UBS 轉換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| PCM1721 | 制造商:BB 制造商全稱:BB 功能描述:DIGITAL-TO-ANALOG CONVERTER WITH PROGRAMMABLE PLL |
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