
SLES010D – SEPTEMBER 2001 – REVISED MAY 2004
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5
Terminal Functions
PCM1772PW
TERMINAL
NAME
AGND1
AGND2
AIN
BCK
I/O
DESCRIPTIONS
NO.
5
6
10
3
—
—
I
I/O
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with the output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from external device. In master interface mode, the PCM1772 device generates the BCK output to an external device.
DATA
LRCK
2
1
I
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
I/O
MC
MD
MS
PD
14
13
15
4
I
I
I
I
SCKI
VCC1
VCC2
VCOM
16
12
11
7
I
System clock input
Power supply for all analog circuits except the lineout amplifier.
Analog power supply for the lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-
μ
F capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
L-channel analog signal output of the lineout amplifiers
R-channel analog signal output of the lineout amplifiers
—
—
—
VOUTL
VOUTR
PCM1772RGA
TERMINAL
NAME
AGND1
AGND2
AIN
BCK
9
8
O
O
I/O
DESCRIPTIONS
NO.
4
5
10
2
—
—
I
I/O
Analog ground. This is a return for VCC1.
Analog ground. This is a return for VCC2.
Monaural analog signal mixer input. The signal can be mixed with output of L- and R-channel DACs.
Serial bit clock. Clocks the individual bits of the audio data input, DATA. In the slave interface mode, this clock is input
from an external device. In the master interface mode, the PCM1772 device generates the BCK output to an external
device.
Serial audio data input
Left and right clock. Determines which channel is being input on the audio data input, DATA. The frequency of LRCK
must be the same as the audio sampling rate. In the slave interface mode, this clock is input from an external device.
In the master interface mode, the PCM1772 device generates the LRCK output to an external device.
Mode control port serial bit clock input. Clocks the individual bits of the control data input, MD.
Mode control port serial data input. Controls the operation mode on the PCM1772 device.
Mode control port select. The control port is active when this terminal is low.
No connect
DATA
LRCK
1
20
I
I/O
MC
MD
MS
NC
14
13
15
I
I
I
8, 17,
18, 19
—
PD
3
I
Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default
settings.
SCKI
VCC1
VCC2
VCOM
16
12
11
6
I
System clock input
Power supply for all analog circuits except lineout amplifier.
Analog power supply for lineout amplifier circuits. The voltage level must be the same as VCC1.
Decoupling capacitor connection. An external 10-
μ
F capacitor connected from this terminal to analog ground is
required for noise filtering. Voltage level of this terminal is 0.5 VCC2 nominal.
R-channel analog signal output of lineout amplifiers.
L-channel analog signal output of lineout amplifiers.
—
—
—
VOUTR
VOUTL
7
9
O
O