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參數資料
| 型號： | PCM3001 |
| 元件分類： | Codec |
| 英文描述： | Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM |
| 中文描述： | 立體聲音頻編解碼器18位，串行接口商標 |
| 文件頁數： | 18/21頁 |
| 文件大小： | 212K |
| 代理商： | PCM3001 |
18
PCM3000/3001
PROGRAM REGISTER 3
A (1:0):
Bit 10, 9
These bits define the address for REGISTER 3:
Register Address
A1
A0
1
1
Register 3
res:
Bit 15:11, 8:6, 0
These bits are reserved, and should be set to “0”.
Audio Data Format Select
These bits determine the input and output audio
data formats. (default: FMT [2:0] = 000
H
)
Reserved
FMT (2:0)
Bit 4:2
FMT2 FMT1 FMT0
DAC
ADC
Data Format
Data Format
0
0
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Left-justified
0
0
1
18-bit, MSB-first,
Right-justified
18-bit, MSB-first,
Left-justified
0
1
0
16-bit, MSB-first,
Right-justified
16-bit, MSB-first,
Right-justified
0
1
1
18-bit, MSB-first,
Right-justified
18-bit, MSB-first,
Right-justified
1
0
0
16-/18-bit, MSB-first,
Left-justified
18-bit, MSB-first,
Left-justified
1
0
1
16-/18-bit, MSB-first, I
2
S
18-bit, MSB-first, I
2
S
1
1
0
16-bit, MSB-first,
DSP-frame
Reserved
16-bit, MSB-first,
DSP-frame
Reserved
1
1
1
LOP:
Bit 5
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I
2
S. In Format 6 (DSP Frame), Loop-
back is not supported.
ADC to DAC Loop-back Control
LOP
0
1
Loop-back Disable (default)
Loop-back Enable
LRP:
Bit 1
Polarity of LRCIN Applies only to
Formats 0 through 4.
LRP
0
1
Left-Channel is “H”, Right-Channel is “L”. (default)
Left-Channel is “L”, Right-Channel is “H”.
PCM3001 DATA FORMAT CONTROL
The input and output data formats are controlled by pins 27
(FMT0), 26 (FMT1), and 25 (FMT2). Set these pins to the
same values shown for the bit-mapped PCM3000 controls in
PROGRAM REGISTER 3.
BYPS:
Bit 7
ADC High-Pass Filter Bypass Control
This bit determines enables or disables the high-
pass filter for the ADC.
BYPS
0
1
High-Pass Filter Enabled (default)
High-Pass Filter Disabled (bypassed)
ATC:
Bit 5
When set to “1”, the REGISTER 0 attenuation
data can be used for both DAC channels. In this
case, the REGISTER 1 attenuation data is ig-
nored.
DAC Attenuation Channel Control
ATC
0
1
Individual Channel Attenuation Data Control (default)
Common Channel Attenuation Data Control
IZD:
Bit 4
DAC Infinite Zero Detection Circuit
Control
This bit enables the Infinite Zero Detection Circuit
in PCM3000. When enabled, this circuit will dis-
connect the analog output amplifier from the delta-
sigma DAC when the input is continuously zero for
65,536 consecutive cycles of BCKIN.
IZD
0
1
Infinite Zero Detection Disabled (default)
Infinite Zero Detection Enabled
OUT:
Bit 3
When set to “1”, the outputs are forced to V
CC
/2
(bipolar zero). In this case, all registers in
PCM3000 hold the present data. Therefore, when
set to “0”, the outputs return to the previous
programmed state.
DAC Output Enable Control
OUT
0
1
DAC Outputs Enabled (default normal operation)
DAC Outputs Disabled (forced to BPZ)
DM (1:0):Bit 2,1
DAC De-emphasis Control
These bits select the de-emphasis mode as shown
below:
DM1
DM0
0
0
1
1
0
1
0
1
De-emphasis OFF (default)
De-emphasis 48kHz ON
De-emphasis 44.1kHz ON
De-emphasis 32kHz ON
MUT:
Bit 0
When set to “1”, both left and right-channel DAC
outputs are muted at the same time. This muting
is done by attenuating the data in the digital filter,
so there is no audible click noise when soft mute
is turned on.
DAC Soft Mute Control
MUT
0
1
Mute Disable (default)
Mute Enable
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| PCM3001E | 功能描述:接口—CODEC SoundPlus Ster Codec 18-bits Ser Intrfc RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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