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參數資料
| 型號： | PCM66P |
| 英文描述： | 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位CMOS單片音頻數字模擬轉換器 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 92K |
| 代理商： | PCM66P |
PCM66P
3
PCM66P PIN ASSIGNMENTS
PIN
DESCRIPTION
MNEMONIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Left/Right Clock
Word Clock
Clock Input
Data Input
No Connection
Digital Common
Analog Common
Left Channel V
OUT
Output Common
Right Channel V
OUT
Analog Supply
Analog Supply
Reference Decouple
Reference Sense
Reference Output
Analog Supply
Analog Supply
Digital Supply
Single DAC Mode
Left/Right DAC Select
LRCLK
WDCLK
CLK
DATA
NC
D
COM
A
L CH Out
V
R CH Out
+V
CC
+V
CC
C
REF
V
REF
SENSE
V
REF
+V
CC
+V
CC
+V
SDM SEL
LRDAC
MODEL
Basic Model Number
1–24
25-99
100+
PCP: Plastic
Performance Grade Code
$11.80
13.30
$10.40
11.70
$9.15
10.30
USA OEM PRICES
PCM66P
-X
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage ............................................................................
±
10V
Input Voltage Range ........................................................... –3V to +5.25V
Power Dissipation ............................................................................ 50mW
Operating Temperature ....................................................–30
°
C to +70
°
C
Storage Temperature......................................................–60
°
C to +100
°
C
Lead Temperature (soldering, 10s) ............................................... +300
°
C
PACKAGE INFORMATION
(1)
PACKAGE DRAWING
NUMBER
MODEL
PACKAGE
PCM66P
PCM66P, J
20-Pin SOIC
20-Pin SOIC
248
248
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
SERIAL
DATA WORD
INPUT
LEFT
CHANNEL
OUTPUT
RIGHT
CHANNEL
OUTPUT
SDM SEL
LRDAC
LRCLCK
WDCLK
0
0
0
0
X
X
X
X
0
0
1
1
0
1
0
1
Right
Right
Left
Left
Hold
Integrate
Hold
Hold
Hold
Hold
Hold
Integrate
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
Inhibited
Inhibited
Left
Left
V
COM
V
COM
V
COM
V
COM
V
COM
V
COM
V
COM
V
COM
Hold
Hold
Integrate
Integrate
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Right
Right
Inhibited
Inhibited
Hold
Hold
Integrate
Integrate
TABLE I. PCM66P Logic Truth Table.
NOTE: Positive edge of CLK (P3) latches LRCLK (P1), WDCLK (P2), and DATA (P4).
PIN FUNCTIONS
THEORY OF OPERATION
The PCM66P is a dual output, 16-bit CMOS digital-to-analog
audio converter. The PCM66P, complete with internal refer-
ence, has two glitch-free voltage outputs and requires only a
single +5V power supply. Output modes using either one or two
channels per DAC are user selectable. The PCM66P accepts a
serial data input format that is compatible with other Burr-
Brown PCM products such as the industry standard PCM56P.
ONE DAC TWO-CHANNEL OPERATION
Normally, the PCM66P is operated with a continuous clock
input in a two-channel output mode. This mode is selected when
SDM SEL is held low (single DAC mode select). Refer to the
truth table shown by Table I for exact control logic relation-
ships. Data for left and right channel output is loaded
alternately into the PCM66P while the control logic
switches the left and right output amplifiers between the
appropriate integrate and hold modes. Data word latch-
ing is controlled by WDCLK (word clock) and channel
selection is made by LRCLK (left/right clock). Figure 1
shows the timing for the single DAC two-channel mode
of operation. The block diagram in Figure 2 shows how
a single DAC output provides switched output to both
integrate and hold amplifiers. Output between left and
right channels in this mode is not in phase. See Figure 3
for proper connection of the PCM66P in the two-channel
DAC mode.
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