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參數資料
| 型號： | PDI1394P11ABD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3-port physical layer interface |
| 中文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數： | 18/20頁 |
| 文件大小： | 135K |
| 代理商： | PDI1394P11ABD |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
18
23.0
When data is received by the phy from the serial bus, it will transfer the data to the link for further processing. The phy will assert ‘Receive’ on
the CTL lines and ‘1’ on each D pin. The phy indicates the start of the packet by placing the speed code on the data bus. The phy will then
proceed with the transmittal of the packet to the link on the D lines while still keeping the ‘Receive’ status on the CTL pins. Once the packet has
been completely transferred, the phy will assert ‘Idle’ on the CTL pins which will complete the receive operation.
RECEIVE
NOTE
: The speed is a phy-link protocol and not included in the CRC.
23.1
RECEIVE TIMING WAVEFORMS
SV00234
00
PHY
CTL [0:1]
10
10
10
00
10
10
10
00
0000
PHY
D [0:3]
1111
P
1
P
n
0000
1111
SPD
P
0
0000
NOTE:
SPD = Speed Code
P
0
P
n
= Packet Data
NOTE:
SPD = Speed Code
P
0
Pn = packet data
Figure 11.
Receive Timing Waveforms
The speed code for the receiver is as follows:
D [0:3]
DATA RATE
(Mbit/s)
00XX
100
0100
NOTE:
X transmitted as 0, ignored on receive.
200
24.0
The settings of the PC[0:2] pins appear in the pwr field of the self–ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23.
POWER CLASS BITS IN SELF–ID PACKET
pwr[21:23]
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self powered, and provides a minimum of 15 W to the bus.
010
Node is self powered, and provides a minimum of 30 W to the bus.
011
Node is self powered, and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus, and is using up to 1 W.
101
Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers.
110
Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers.
111
Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PDI1394P11ABD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| PDI1394P11BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11BD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| PDI1394P21 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
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