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參數資料
| 型號： | PDM41257LA8SO |
| 廠商： | IXYS CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 1 STANDARD SRAM, 8 ns, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-24 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 257K |
| 代理商： | PDM41257LA8SO |
Rev. 2.2 - 4/27/98
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Features
n High-speed access times
Com’l: 7, 8, 10, 12 and 15 ns
Industrial: 8, 10, 12 and 15 ns
n Low power operation (typical)
- PDM41257SA
Active: 400 mW
Standby: 150 mW
- PDM41257LA
Active: 350 mW
Standby: 25 mW
n Single +5V (±10%) power supply
n TTL compatible inputs and outputs
n Packages
Plastic SOJ (300 mil) - SO
Description
The PDM41257 is a high-performance CMOS static
RAM organized as 262,144 x 1 bit. Writing to this
device is accomplished when the write enable (WE)
and the chip enable (CE) inputs are both LOW.
Reading is accomplished when WE remains HIGH
and CE goes LOW.
The PDM41257 operates from a single +5V power
supply and all the inputs and outputs are fully TTL-
compatible. The PDM41257 comes in two versions,
the standard power version PDM41257SA and a low
power version the PDM41257LA. The two versions
are functionally the same and only differ in their
power consumption.
The PDM41257 is available in a 24-pin 300-mil
plastic SOJ for surface mount applications.
A0
A17
CE
WE
Addresses
Decoder
Memory
Matrix
Column I/O
DIN
DOUT
Functional Block Diagram
PDM41257
256K Static RAM
256K x 1-Bit
相關PDF資料 |
PDF描述 |
|---|---|
| PDM41257SA10SOTR | 256K X 1 STANDARD SRAM, 10 ns, PDSO24 |
| P4C1682-35JC | 4K X 4 STANDARD SRAM, 35 ns, PDSO24 |
| P4C180-12PC | 4K X 4 CACHE TAG SRAM, 12 ns, PDIP22 |
| P4C1682-35PC | 4K X 4 STANDARD SRAM, 35 ns, PDIP24 |
| P4C170-12JI | 4K X 4 STANDARD SRAM, 12 ns, PDSO22 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PDM41257LA8SOI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| PDM41257LA8SOITR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| PDM41257LA8SOITY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| PDM41257LA8SOTR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| PDM41257LA8SOTY | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
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