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參數資料
| 型號： | PDU53-500MC3 |
| 英文描述： | Delay Line |
| 中文描述： | 延遲線 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 264K |
| 代理商： | PDU53-500MC3 |
PDU53
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU53)
data
delay
devices,
inc.
3
FEATURES
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 100K-ECL interfaced & buffered
Available in 16-pin DIP (600 mil) socket or SMD
PACKAGES
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
IN
A2
A1
VEE
A0
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
IN
A2
A1
VEE
A0
N/C
N/C
N/C
FUNCTIONAL DESCRIPTION
The PDU53-series device is a 3-bit digitally programmable delay line. The
delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends on the
address code (A2-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The
address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance:
5% or 40ps,
whichever is greater
Inherent delay (TD
0
):
2.2ns typical
Address to input setup (T
AIS
):
2.9ns
Operating temperature:
0
°
to 85
°
C
Temperature coefficient:
100PPM/
°
C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
±
0.7V
Power Supply Current:
-150ma typical (50
to -2V)
Minimum pulse width:
3ns or 15% of total delay,
whichever is greater
Minimum period:
8ns or 2 x pulse width, whichever
is greater
A2-A0
A
i-1
A
i
PDU53-xx
PDU53-xxM Military DIP
DIP
PDU53-xxC3
PDU53-xxMC3 Mil SMD
SMD
PIN DESCRIPTIONS
IN
Signal Input
OUT Signal Output
A2
Address Bit 2
A1
Address Bit 1
A0
Address Bit 0
VEE -5 Volts
GND Ground
DASH NUMBER SPECIFICATIONS
Part
Number
Per Step (ps)
PDU53-100
100
±
50
PDU53-200
200
±
60
PDU53-250
250
±
60
PDU53-400
400
±
80
PDU53-500
500
±
100
PDU53-750
750
±
100
PDU53-1000
1000
±
200
PDU53-1200
1200
±
200
PDU53-1500
1500
±
200
PDU53-2000
2000
±
400
PDU53-2500
2500
±
400
PDU53-3000
3000
±
500
NOTE: Any dash number between 100 and 3000
not shown is also available.
Incremental Delay
Total Delay
Change (ns)
0.70
1.40
1.75
2.80
3.50
5.25
7.00
8.40
10.50
14.00
17.50
21.00
T
OAX
PW
IN
TD
A
PW
OUT
IN
OUT
Figure 1: Timing Diagram
T
AIS
1997 Data Delay Devices
Doc #98003
3/18/98
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
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| PDU53-750 | Programmable Delay Line |
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| PDU53SERIES | 3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PDU53-750 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53-750C3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53-750M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53-750MC3 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) |
| PDU53SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-BIT. ECL-INTERFACED PROGRAMMABLE DELAY LINE |
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