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參數資料
| 型號： | PEELTM16CV8S-25 |
| 英文描述： | ASIC |
| 中文描述： | 專用集成電路 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 173K |
| 代理商： | PEELTM16CV8S-25 |
1
04-02-004I
Commercial
The PEEL
TM
16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. ICT’s PEEL
TM
16CV8
can be programmed with existing 16CV8 JEDEC file. Some program-
mers also allow the PEEL
TM
16CV8 to be programmed directly from
PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional development
and programmng support for the PEEL
TM
16CV8 is provided by popular
third-party programmers and development software. ICT also offers free
PLACE development software.
General Description
The PEEL
TM
16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEEL
TM
16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEEL
TM
16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as
low as 37mA. EE-Reprogrammability provides the convenience of
instant reprogrammng for development and reusable production inven-
tory mnimzing the impact of programmng changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
PEEL 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Features
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces randomlogic
- Super sets standard 20-pin PLDs (PALs)
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
Figure 1 - Pin Configuration
DIP
I/CLK1
1
2
3
4
5
6
7
8
9
10
I
I
I
I
I
I
I
I
GND
11
I
12
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
I/CLK1
I
I
I
I
I
I
I
I
GND
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TSSOP
1
2
3
4
5
6
7
8
9
10
I/CLK1
I
I
I
I
I
I
I
I
GND
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SOIC
4
5
6
7
8
I
I
I
I
I
9
I
10
G
11
I
12
I
13
I
3
I
2
I
1
I
V
19
I
PLCC-J
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
20
Figure 2 - Block Diagram
64 TX
32 INPUTS
PEEL
"AND"
ARRAY
C LK
MAC RO
C ELL
/C LK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/OE
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相關代理商/技術參數 |
參數描述 |
|---|---|
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