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參數資料
| 型號： | PEX8548-AA25BI |
| 廠商： | PLX Technology, Inc. |
| 英文描述： | High-Performance 48-lane, 9-port PCIe Switch |
| 中文描述： | 高性能48通道，9端口PCIe交換器 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 320K |
| 代理商： | PEX8548-AA25BI |
High-Performance 48-lane, 9-port PCIe Switch
Features
PEX 8548 General Features
o
48-lane PCI Express switch
-
Integrated SerDes
o
Up to nine configurable ports
(x1, x2, x4, x8, x16)
o
37.5mm x 37.5mm,
736-ball PBGA package
o
Typical Power: 4.9 Watts
PEX 8548 Key Features
o
Standard Compliant
-
PCI Express Base Specification, r1.1
o
High Performance
-
Non-blocking switch fabric
-
Full line rate on all ports
-
Packet Cut-Thru with 110ns max
packet latency (x16 to x16)
o
Flexible Configuration
-
Nine highly flexible & configurable
ports (x1, x2, x4, x8, or x16)
-
Configurable with strapping pins,
EEPROM, I
2
C, or Host software
-
Lane and polarity reversal
o
PCI Express Power Management
-
Link power management states: L0,
L0s, L1, L2/L3 Ready, and L3
-
Device states: D0 and D3hot
o
Quality of Service (QoS)
-
One Virtual Channel per port
-
Eight Traffic Classes per port
-
Weighted Round-Robin Ingress Port
Arbitration
o
Reliability, Availability, Serviceability
-
3 Standard Hot-Plug Controllers
-
Upstream port as hot-plug client
-
Transaction Layer end-to-end CRC
-
Poison bit
-
INTA# interrupt signal
-
Fatal Error (FATAL_ERR#) signal
(legacy SERR equivalent)
-
PCIe baseline error reporting
-
Advanced Error Reporting
-
Port Status bits and GPO available
-
Per port error diagnostics
Bad DLLPs
Bad TLPs
CRC errors
-
JTAG boundary scan
Multi-purpose, High Performance
ExpressLane
Switch
The
ExpressLane
PEX 8548 device offers PCI Express switching capability
enabling users to add scalable high bandwidth, non-blocking interconnection
to a wide variety of applications including
servers, storage systems,
communications platforms, blade servers,
and
embedded-control
products
. The PEX 8548 is well suited for
fan-out
,
aggregation, dual-
graphics, peer-to-peer,
and
fabric backplane
applications.
Highly Flexible Port Configurations
The PEX 8548 offers highly configurable ports. There are a maximum of 9
ports that can be configured to any legal width from x1 to x16, in any
combination to support your specific bandwidth needs. The ports can be
configured for
symmetric
(each port having the same lane width and traffic
load) or
asymmetric
(ports having different lane widths) traffic. In the event
of asymmetric traffic, the PEX 8548 features a
flexible central packet
memory
that allocates a memory buffer for each port as required by the
application or endpoint. This buffer allocation along with the device's
flexible packet flow control
minimizes bottlenecks when the upstream and
aggregated downstream bandwidths do not match (are asymmetric). Any of
the ports can be designated as the upstream port, which can be changed
dynamically.
High Performance
The PEX 8548 architecture supports packet
cut-thru with a max latency of
110ns (x16 to x16).
This, combined with large packet memory
(1024 byte
maximum payload size)
and non-blocking internal switch architecture,
provide full line rate on all ports for performance-hungry applications such as
storage servers
or
storage switch fabrics
.
End-to-end Packet Integrity
The PEX 8548 provides
end-to-end CRC
protection (ECRC) and
Poison
bit
support to enable designs that require
end-to-end data integrity
. These
features are optional in the PCI Express specification, but PLX provides
them across its entire
ExpressLane
switch product line.
Configuration Flexibility
The PEX 8548 provides several ways to configure its operations. The device
can be configured through strapping pins,
I
2
C interface
, CPU configuration
cycles, or an optional serial EEPROM. This allows for easy debug during the
development phase, performance monitoring during the operation phase, and
driver or software upgrade.
Interoperability
The PEX 8548 is designed to be fully compliant with the PCI Express Base
Specification r1.1. Additionally, it supports
auto-negotiation
,
lane reversal
,
and
polarity reversal
. The PEX 8548 also undergoes thorough
interoperability testing in PLX’s
Interoperability Lab
.
PEX 8548
Version 1.5 2007
相關PDF資料 |
PDF描述 |
|---|---|
| PEX8548-AA25BIG | High-Performance 48-lane, 9-port PCIe Switch |
| PEX8548-AARDK | High-Performance 48-lane, 9-port PCIe Switch |
| PEX8612 | PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch |
| PEX8612-AA50BCG | PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch |
| PEX8612-AARDK | PCIe Gen2, 5.0GT/s 12-lane, 3-port Switch |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PEX8548-AA25BI G | 制造商:PLX Technology 功能描述:PCIE 48-LANE 9-PORT SWITCH BGA 制造商:PLX Technology 功能描述:PCIE, 48-LANE, 9-PORT SWITCH, BGA |
| PEX8548-AA25BIG | 功能描述:外圍驅動器與原件 - PCI 48 Lane 9 Port PCI Express Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PEX8548-AARDK | 功能描述:界面開發工具 Rapid Dev Kit For PEX 8548 RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PEX8603-AA50NI-G | 功能描述:外圍驅動器與原件 - PCI 3 lane 3 port Gen 2 PCIe Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PEX8603-AB50NI G | 功能描述:PCI Express? Switch IC 3 Channel 136-aQFN (10x10) 制造商:broadcom limited 系列:- 包裝:托盤 零件狀態:在售 應用:PCI Express? 多路復用器/解復用器電路:- 開關電路:- 通道數:3 導通電阻（最大值）:- 電壓 -?電源，單（V+）:- 電壓 - 電源，雙（V±）:- -3db 帶寬:- 特性:- 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:- 供應商器件封裝:136-aQFN（10x10） 標準包裝:840 |
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