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參數資料
型號: PHB45N03LTA
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: N-channel enhancement mode field-effect transistor
中文描述: 40 A, 25 V, 0.024 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: PLASTIC, D2PAK-3
文件頁數: 1/8頁
文件大小: 61K
代理商: PHB45N03LTA
Philips Semiconductors
Product specification
TrenchMOS
transistor
Logic level FET
PHB45N03LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 30 V
’Trench’
technology
Very low on-state resistance
Fast switching
Stable off-state characteristics
High thermal cycling performance
Low thermal resistance
Surface mounting package
I
D
= 45 A
R
DS(ON)
24 m
(V
GS
= 5 V)
R
DS(ON)
21 m
(V
GS
= 10 V)
GENERAL DESCRIPTION
PINNING
SOT404
N-channel
logic
transistor in a plastic envelope
using ’
trench
’ technology. The
device
has
very
resistance. It is intended for use in
dc to dc converters and general
purpose switching applications.
enhancement
field-effect
mode
power
PIN
DESCRIPTION
level
1
gate
low
on-state
2
drain (no connection
possible)
3
source
ThePHB45N03LTissuppliedinthe
SOT404
surface
package.
tab
drain
mounting
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
30
30
15
45
36
180
86
175
UNIT
V
V
V
A
A
A
W
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
TYP.
-
MAX.
1.75
UNIT
K/W
R
th j-a
pcb mounted, minimum
footprint
50
-
K/W
d
g
s
1
3
mb
2
December 1997
1
Rev 1.300
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