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參數(shù)資料
| 型號： | PHD3N20L |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistor Logic level FET |
| 中文描述： | 3.5 A, 200 V, 1.5 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | PLASTIC PACKAGE-3 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 56K |
| 代理商： | PHD3N20L |
Philips Semiconductors
Product specification
PowerMOS transistor
Logic level FET
PHD3N20L
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermalcyclingperformancewithlow
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
applications.
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
200
3.5
50
1.5
V
A
W
switching
PINNING - SOT428
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
Continuous drain current
CONDITIONS
T
mb
= 25 C; V
GS
= 10 V
T
mb
= 100 C; V
GS
= 10 V
T
mb
= 25 C
T
mb
= 25 C
T
mb
> 25 C
MIN.
-
-
-
-
-
-
-
MAX.
3.5
2.5
14
50
0.33
±
15
±
20
UNIT
A
A
A
W
W/K
V
V
I
DM
P
D
P
D
/
T
mb
Linear derating factor
V
GS
Gate-source voltage
V
GSM
Non-repetitive gate-source
voltage
E
AS
Single pulse avalanche
energy
I
AS
Peak avalanche current
Pulsed drain current
Total dissipation
t
p
≤
50
μ
s
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 5 V
V
DD
≤
50 V; starting T
j
= 25C; R
GS
= 50
;
V
GS
= 5 V
-
25
mJ
-
3.5
A
T
j
, T
stg
Operating junction and
storage temperature range
- 55
175
C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
MAX.
3
UNIT
K/W
R
th j-a
pcb mounted, minimum
footprint
50
-
K/W
1
2
3
tab
d
g
s
September 1997
1
Rev 1.000
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