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參數(shù)資料
| 型號(hào)： | PI6C2302W |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Phase-Locked Loop Clock Driver |
| 中文描述： | 鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大?。?/td> | 279K |
| 代理商： | PI6C2302W |
1
PS8418B 05/21/01
1
2
3
AV
CC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
V
CC
S
Product Pin Configuration
Logic Block Diagram
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Product Features
2X CLK_IN on CLK_OUT
High-Performance Phase-Locked-Loop Clock Distribution
for Networking, ATM, 100/134 MHz Registered DIMM
Synchronous DRAM modules for server/workstation/
PC applications
Zero Input-to-Output delay
Low jitter: Cycle-to-Cycle jitter ±100ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
CC
Wide range of Clock Frequencies
Package:
Plastic 8-pin SOIC Package (W)
Product Description
The PI6C2302 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero. The PI6C2302
provides 2X CLK_IN on CLK_OUT output.
Application
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-
to-device skew introduced can significantly reduce the perfor-
mance. Pericom recommends the use of a zero-delay buffer and an
eighteen output non-zero-delay buffer. As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
17
Zero Delay
Buffer
PI6C2302
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
Control Input
S
e
u
o
S
t
p
O
n
w
o
d
h
S
L
L
P
1
L
L
P
N
0
N
I
K
L
C
Y
CLK_IN
FB_IN
S
PLL
CLK_OUT
÷2
8-Pin
W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C2305-1 | 3.3V Zero-Delay Buffer |
| PI6C2305-1HW | 3.3V Zero-Delay Buffer |
| PI6C2305-1HWI | 3.3V Zero-Delay Buffer |
| PI6C2305-1W | 3.3V Zero-Delay Buffer |
| PI6C2305-1WI | 3.3V Zero-Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2302-WI | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver |
| PI6C2305-1 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer |
| PI6C2305-1HW | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer |
| PI6C2305-1HWI | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer |
| PI6C2305-1W | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Zero-Delay Buffer |
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