參數資料
| 型號： | PI6C2402WE |
| 廠商： | Pericom |
| 文件頁數： | 1/4頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK DRIVER 8-SOIC |
| 產品培訓模塊： | Total Timing Technology |
| 標準包裝： | 97 |
| 類型： | PLL 時鐘驅動器 |
| PLL： | 帶旁路 |
| 輸入： | TTL |
| 輸出： | TTL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 134MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
1
PS8418I
11/13/08
Pin Conguration
Block Diagram
PI6C2402
Features
Clock doubler
High-Performance Phase-Locked-Loop Clock Distribution for
Networking, ATM, 100 MHz and 134 MHz Registered DIMM
Synchronous DRAM modules for server, workstation, and PC
applications
Zero Input-to-Output delay
Cycle-to-Cycle jitter ≤ ±150ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V VCC
Packaging (Pb-free & Green available):
— 8-pin SOIC Package (W)
Phase-Locked Loop Clock Driver
Description
The PI6C2402 features a low-skew, low-jitter, Phase-Locked Loop
(PLL) clock driver. By connecting the feedback CLK_OUT out-
put to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.The PI6C2402
provides 2X CLK_IN on CLK_OUT output.
Applications
If the system designer needs more than 16 outputs with the fea-
tures just described, using two or more zero-delay buffers such
as the PI6C2509, and the PI6C2510, are likely to be impractical.
The device-to-device skew introduced can signicantly reduce
the performance. Pericom recommends the use of a zero-delay
buffer and an eighteen output non-zero-delay buffer. As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. Zero-Delay Buffering Diagram
17
Zero Delay
Buffer
PI6C2402
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
Control Input
S
Outputs Source
PLL Shutdown
HIGH
PLL
Disabled
LOW
CLK_IN
Enabled
CLK_IN
FB_IN
S
PLL
CLK_OUT
÷2
1
2
3
AVCC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
VCC
S
08-0298
相關PDF資料 |
PDF描述 |
|---|---|
| PI6C2405A-1WIE | IC 1:5 0-DELAY CLOCK BUFF 8-SOIC |
| PI6C2408-4WIE | IC 4+4 0-DELAY CLK BUFF 16-SOIC |
| PI6C2409-1WE | IC 4+4+1 0-DELAY CLK BUFF 16SOIC |
| PI6C2501AWE | IC PLL CLOCK DRIVER 8-SOIC |
| PI6C2501WE | IC PLL CLOCK DRIVER 8-SOIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PI6C2402WEX | 功能描述:鎖相環 - PLL 3.3v Zero Delay Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2404A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Zero-Delay Clock Buffer |
| PI6C2404A-1 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Zero-Delay Clock Buffer |
| PI6C2404A-1I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 2+2 Output Zero-Delay Clock Driver. 10 to 133 MHz |
| PI6C2404A-1W | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Buffer Single 8-Pin SOIC |
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