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參數資料
| 型號： | PI6C2972 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Low Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時鐘驅動器 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 184K |
| 代理商： | PI6C2972 |
1
PS8590C 09/22/04
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PI6C2972
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver devices
targeted for high-performance CISC or RISC processor based sys-
tems. With output frequencies of up to 125 MHz and skews of 550ps
the PI6C2972 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
The PI6C2972 features an extensive level of frequency programma-
bility between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
Power–On Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after power–up to ensure synchroni-
zation between the QFB output and the other outputs. The internal
power–on reset is designed to provide this function, but with
power–up conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
during PLL lock acquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal pull–
up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS/LVTTL compatible
levels while the outputs provide LVCMOS levels with the capability
to drive 50-ohm transmission lines. For series terminated lines each
PI6C2972 output can drive two 50-ohm lines in parallel thus effec-
tively doubling the fanout of the device.
Features
Fully Integrated PLL
Output Frequency up to 125 MHz
Compatible with PowerPC and Pentium Microprocessors
3.3V V
CC
+ 100ps Typical Cycle–to–Cycle Jitter
Packaging (Pb-free & Green available):
- 52-pin LQFP (FC)
Low Voltage PLL Clock Driver
Pin Configuration
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
1 2 3 4 5 6 7 8 9 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
G
Q
V
Q
G
Q
V
Q
E
G
Q
V
f
G
M
F
F
f
P
R
T
T
T
x
x
V
相關PDF資料 |
PDF描述 |
|---|---|
| PI6C2972FC | Low Voltage PLL Clock Driver |
| PI6C2972FCE | Low Voltage PLL Clock Driver |
| PI6C3420A | 27 MHz Spread Spectrum Clock Synthesizer |
| PI6C3420ATE | 27 MHz Spread Spectrum Clock Synthesizer |
| PI6C39911 | 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PI6C2972FC | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C2972FCE | 功能描述:鎖相環 - PLL Zero Delay Buffer with Divider RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2972FCEX | 功能描述:鎖相環 - PLL Zero Delay Buffer with Divider RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2973 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 3.3V. 125MHz. Selectable LVTTL/LVCMOS & LVPECL Inputs. Zero Delay Clock Driver w/ Programmable Divider |
| PI6C3420A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:27 MHz Spread Spectrum Clock Synthesizer |
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