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參數(shù)資料
| 型號： | PI6C39911-2 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Clock IC | 250ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
| 中文描述： | 時鐘IC |為250ps精度。 3.3。 LVTTL等級。 3.75至110 MHz |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 262K |
| 代理商： | PI6C39911-2 |
1
PS8497E 09/13/02
Features
All output pair skew <100ps typical (250 Max.)
12.5 MHz to 133 MHz output operation
3.125 MHz to 133 MHz input operation (input as low as 3.125
MHz for 4x operation, or 6.25 MHz for 2x operation)
User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at and input frequency
— Operation at 2X and 4X input frequency
Zero input-to-output delay
50% duty-cycle outputs
Inputs are 5V Tolerant
LVTTL outputs drive 50-Ohm terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
Pin Configuration
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
3
V
C
F
V
C
2
2
3
F
V
C
R
G
T
2
4
3
2
1
32 31
30
14 15 16 17 18 19
20
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3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer -
SuperClock
32 Pin
J
1Q0
1Q1
1F0
1F1
2Q0
2Q1
2F0
2F1
3Q0
3Q1
3F0
3F1
4Q0
4Q1
4F0
4F1
Select Inputs
(three level)
Matrix
Select
Skew
Test
Filter
Phase
Freq.
DET
FB
REF
FS
VCO and
Time Unit
Generator
相關PDF資料 |
PDF描述 |
|---|---|
| PI6C39911-5 | Clock IC | 500ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
| PI6C410B | Clock Generator for Intel PCI-Express Server Chipset |
| PI6C410BAE | Clock Generator for Intel PCI-Express Server Chipset |
| PI6C410BVE | Clock Generator for Intel PCI-Express Server Chipset |
| PI6C410M | Clock Generator for Intel PCI Express Mobile Chipset |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C39911-2J | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock |
| PI6C39911-2JE | 功能描述:鎖相環(huán) - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C39911-2JEX | 功能描述:鎖相環(huán) - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C39911-5 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Clock IC | 500ps Accuracy. 3.3V. LVTTL. 3.75 to 110 MHz |
| PI6C39911-5J | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay Programmable PLL Clock Buffer Single 12.5MHz to 133MHz 32-Pin PLCC |
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