參數資料
| 型號： | PI74AVC+16836A |
| 廠商： | Pericom |
| 文件頁數： | 1/10頁 |
| 文件大小： | 0K |
| 描述： | IC UNIV BUS DVR 20BIT 56TSSOP |
| 產品變化通告： | Product Discontinuation Notice 11/Feb/2008 |
| 標準包裝： | 35 |
| 系列： | 74AVC+ |
| 邏輯類型： | 通用總線驅動器 |
| 電路數： | 20 位 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 56-TSSOP |
| 包裝： | 管件 |
1
PS8511E
10/17/08
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PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Block Diagram
Features
PI74AVC
+16836 is designed for low-voltage operation,
VCC = 1.65V to 3.6V
True ±24mA Balanced Drive @ 3.3V
IOFF supports partial power-down operation
3.6V I/O Tolerant inputs and outputs
Meets PC133 SDRAM Registered DIMM Specifications
All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise without
degrading propagation delay
Industrial operation: –40°C to +85°C
Packaging (Pb-free & Green available):
– 56-pin 240-mil wide plastic TSSOP (A)
Description
Pericom Semiconductor’s 20-bit PI74AVC+16836 universal bus
driver is designed for 1.65V to 3.6V VCC operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is HIGH,
the A data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state, but all the inputs are enabled and data is capable
of being stored in the register.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
OE
CLK
LE
A1
1
56
29
55
1D
CLK
C1
Y1
2
V
TO 19 OTHER CHANNELS
08-0291
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