參數資料
| 型號： | PI90LV211QE |
| 廠商： | Pericom |
| 文件頁數： | 1/7頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:6 28-QSOP |
| 產品變化通告： | Product Discontinuation 23/May/2008 |
| 標準包裝： | 48 |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | LVDS，TTL |
| 輸出： | LVDS |
| 頻率 - 最大： | 250MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-QSOP |
| 包裝： | 管件 |
1
PS8535D
10/27/09
VCC
EN1
EN2
EN3
SEL
EN4
EN5
EN6
CEN
GND
CLK
SCLK
CLK
GND
D
CLK6OUT–
GND
CLK6OUT+
16
15
17
13
14
11
12
9
8
7
6
5
4
3
2
1
10
CLK5OUT–
CLK5OUT+
18
19
CLK4OUT–
CLK4OUT+
20
21
CLK3OUT–
CLK3OUT+
22
23
CLK2OUT–
CLK2OUT+
24
25
CLK1OUT–
CLK1OUT+
VCC
26
27
28
Q
D
Q
D
Q
D
Q
D
Q
D
Q
1
0
PI90LVT211
Only 110W
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Features
Meets or Exceeds Requirements of ANSI TIA/EIA-644-1995
Designed for Clocking Rates up to 320MHz
Operates from a single 3.3-V Supply
Low-Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100-ohm load
Choice between LVDS or TTL clock input
Synchronous Enable/Disable
Multiplexed clock input
– Internal 300 kohm pullup resistor on all control pins
Common and individual Enable/Disable control
50ps Output-to-Output Skew
±24ps Period Jitter
Bus Pins are High Impedance when disabled or with VCC <1.5V
TTL Inputs are 5V Tolerant
Power Dissipation at 300 MHz
P190LV211 is functionally compatible with Motorola’s
(PECL)MC10E211/MC100E211
>12kVESDProtection
Packaging (Pb-free & Green available):
- 28-pin TSSOP (L)
PI90LV211
Block Diagram & Pin Configuration
Description
ThePI90LV211implementslowvoltagedifferentialsignaling(LVDS)
to achieve clocking rates as high as 320 MHz with low skew. The
PI90LV211isalowskew1:6fanoutdevicedesignedexplicitlyforlow
skew clock distribution applications. The device features a multi-
plexed clock input to allow for the distribution of a lower speed scan
or test clock with the high-speed system clock. When LOW the SEL
pin will select the differential clock input.
Both a common enable and individual output enables are provided.
When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enable function is
synchronous so that the outputs will only be enabled/disabled when
they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled
as can happen with an asynchronous control. The internal flip flop
is clocked on the falling edge of the input clock, therefore all
associated specification limits are referenced to the negative edge
of the clock input.
Individual synchronous enable controls and multiplexed clock in-
puts make this device ideal as the first level distribution unit in a
distribution tree. The individual enables could be used to allow for the
disabling of individual cards on a backplane in fault tolerant designs.
K
L
C
/
K
L
CK
L
C
SL
E
Sx
N
EN
E
C)
±
(
T
U
O
K
L
C
L
/
H
X
↓
X
L
/
H
↓
L
H
X
H
L
H
L
H
K
L
C
K
L
C
S
*
Z
*
Z
Function Table
*
ENx disables individual banks
** CEN disables all six banks
↓ = Negative transition of CLK or SCLK
Z = High Impedance
1:6 Differential Clock Distribution Chip
08-0295
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI90LV211QEX | 功能描述:時鐘驅動器及分配 1:6 LVDS Clock Distribution RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| PI90LV3486 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:LVDS High-Speed Differential Line Receivers |
| PI90LV3486L | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:LVDS High-Speed Differential Line Receivers |
| PI90LV3486LE | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:LVDS High-Speed Differential Line Receivers |
| PI90LV3486W | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:LVDS High-Speed Differential Line Receivers |
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