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參數資料
| 型號： | PIC18LF8722-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 80TQFP |
| 產品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 119 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數： | 70 |
| 程序存儲器容量： | 128KB（64K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數據轉換器： | A/D 16x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-TQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 644 (CN2011-ZH PDF) |
2006 Microchip Technology Inc.
DS80221C-page 1
PIC18F6627/6722/8627/8722
The PIC18F6627/6722/8627/8722 parts you have
received conform functionally to the Device Data Sheet
(DS39646B), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F6627/6722/8627/8722 devices will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All of the issues listed here will be addressed in future
revisions of the PIC18F6627/6722/8627/8722 silicon.
The
following
silicon
errata
apply
only
to
PIC18F6627/6722/8627/8722 devices with these
Device/Revision IDs:
1.
Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTAx register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXxIF. This is because any write to the
TXSTAx register results in a reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXxIF is set, either by polling
TXxIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when
a
transmission
is
not
in
progress
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
2.
Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/TMR3L
immediately following a write to TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait for
another event before also updating TMR1L/
TMR3L.
Date Codes that pertain to this issue:
All engineering and production devices.
3.
Module: Timer1/Timer3
When Timer1 or Timer3 is the time base for CCPx,
and the associated CCPxCON register is config-
ured with 0x0B (Compare mode, trigger special
event), the assigned timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer registers
(TMRxL and TMRxH) upon detection of the
compare match condition.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number
Device ID
Revision ID
PIC18F6627
01 0011 110
00000
PIC18F6722
01 0100 000
00000
PIC18F8627
01 0011 111
00000
PIC18F8722
01 0100 001
00000
The Device IDs (DEVID1 and DEVID2) are located at
addresses
3FFFFEh:3FFFFFh
in
the
device’s
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
PIC18F6627/6722/8627/8722 Rev. A1 Silicon Errata
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