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參數(shù)資料
| 型號(hào)： | PL611S-17-XXXUI |
| 廠商： | PhaseLink Corporation |
| 英文描述： | 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| 中文描述： | 1.8 - 3.3V的PicoPLLTM千赫到MHz可編程時(shí)鐘 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 234K |
| 代理商： | PL611S-17-XXXUI |
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 1
FEATURES
Advanced Programmable PLL design for low-
frequency (kHz) input applications.
Input Frequency: 10kHz to 200MHz
OTP selectable AC/DC Input Coupling.
Accepts >0.1V reference signal input voltage
Very low Jitter and Phase Noise
Output Frequency:
o
<65MHz @ 1.8V operation
o
<90MHz @ 2.5V operation
o
<125MHz @ 3.3V operation
Disabled outputs programmable as HiZ or Active Low.
Offered in Tiny
GREEN
/RoHS compliant packages
o
6-pin DFN (2.0mmx1.3mmx0.6mm)
o
6-pin SC70 (2.3mmx2.25mmx1.0mm)
o
6-pin SOT23 (3.0mmx3.0mmx1.35mm)
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
Operating temperature range from -40
°
C to 85
°
C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL
TM
Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
BLOCK DIAGRAM
Charge
Pump
VCO
FIN
Programmable
Function
Phase
Detector
R-Counter
(7-bit)
M-Counter
(16-bit)
P-Counter
(4-bit)
F
VCO
= F
Ref
* (M/R)
CLK0
F
Out
= F
VCO
/2*P
Ref.
Programming
Logic
OE, PDB,
FSEL, CLK1
1
2
3
4
5
6
LF
GND
CLK0
OE, PDB,
FSEL, CLK1
VDD
FIN
DFN-6L
(2.0mmx1.3mmx
mm
SOT23-6L
(3.0mmx3.0mmx135mm)
FIN
VDD
LF
GND
CLK0
OE, PDB, FSEL, CLK1
P
1
2
3
4
5
6
FIN
VDD
GND
SC70-6L
(2.mmx2.25mmx1.mm)
LF
CLK0
P
OE, PDB,
FSEL, CLK1
P
1
2
3
6
5
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PL611S-17-XXXUIR | 制造商:PLL 制造商全稱:PLL 功能描述:1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock |
| PL611S-18 | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
| PL611S-18-XXXGC | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
| PL611S-18-XXXGCR | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
| PL611S-18-XXXGC-R | 制造商:PLL 制造商全稱:PLL 功能描述:0.5kHz-125MHz MHz to KHz Programmable ClockTM |
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