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參數資料
| 型號： | PLDC20G10B-15JC |
| 英文描述： | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| 中文描述： | UV-Erasable/OTP可編程邏輯器件 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 300K |
| 代理商： | PLDC20G10B-15JC |
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相關PDF資料 |
PDF描述 |
|---|---|
| PLDC20G10B-15JI | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C |
| PLDC20G10B-15PI | UV-Erasable/OTP PLD |
| PLDC20G10B-20JC | UV-Erasable/OTP PLD |
| PLDC20G10B-20JI | Clock-Tunable, Quad Second Order, Filter Building Blocks; Package: PDIP; No of Pins: 24; Temperature Range: 0°C to +70°C |
| PLDC20G10B-20LMB | Clock-Tunable, Quad Second Order, Filter Building Blocks; Package: SSOP; No of Pins: 28; Temperature Range: -40°C to +85°C |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PLDC20G10B-15JI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PLDC20G10B-15PC | 制造商:Cypress Semiconductor 功能描述:SPLD PLDC20G10B Family 10 Macro Cells 62.5MHz CMOS Technology 5V 24-Pin PDIP 制造商:Cypress Semiconductor 功能描述:SPLD PLDC20G10B Family 10 Macro Cells 62.5MHz 5V 24-Pin PDIP |
| PLDC20G10B-15PI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
| PLDC20G10B-15WC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CMOS Generic 24-Pin Reprogrammable Logic Device |
| PLDC20G10B-15WI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP PLD |
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