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參數資料
| 型號： | PLHS501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable macro logic(可編程宏邏輯) |
| 中文描述： | 可編程邏輯宏（可編程宏邏輯） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 158K |
| 代理商： | PLHS501 |
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1
A Package
(52-pin PLCC)
I
11
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I
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CC
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0
B
3
B
2
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1
B
0
X
7
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GND
GND
X
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B
7
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Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
1
October 22, 1993
853–1207 11164
FEATURES
Programmable Macro Logic device
Full connectivity
TTL compatible
SNAP development system:
–
Supports third-party schematic entry
formats
–
Macro library
–
Versatile netlist format for design
portability
–
Logic, timing, and fault simulation
Delay per internal NAND function = 6.5ns
(typ)
Testable in unprogrammed state
Security fuse allows protection of
proprietary designs
STRUCTURE
NAND gate based architecture
–
72 foldback NAND terms
136 input-wide logic terms
44 additional logic terms
24 dedicated inputs (I
0
– I
23
)
8 bidirectional I/Os with individual 3-State
enable:
–
4 Active-High (B
4
– B
7
)
–
4 Active-Low (B
0
– B
3
)
16 dedicated outputs:
–
4 Active-High outputs
O
0
, O
1
with common 3-State enable
O
2
, O
3
with common 3-State enable
–
4 Active-Low outputs:
O
4
, O
5
with common 3-State enable
O
6
, O
7
with common 3-State enable
–
8 Exclusive-OR outputs:
X
0
, X
1
with common 3-State enable
X
2
, X
3
with common 3-State enable
X
4
, X
5
with common 3-State enable
X
6
, X
7
with common 3-State enable
PIN CONFIGURATION
DESCRIPTION
The PLHS501 is a high-density Bipolar
Programmable Macro Logic device. PML
incorporates a programmable NAND
structure. The NAND architecture is an
efficient method for implementing any logic
function. The SNAP software development
system provides a user friendly environment
for design entry. SNAP eliminates the need
for a detailed understanding of the PLHS501
architecture and makes it transparent to the
user. PLHS501 is also supported on the
Philips Semiconductors SNAP software
development systems.
The PLHS501 is ideal for a wide range of
microprocessor support functions, including
bus interface and control applications.
The PLHS501 is also processed to industrial
requirements for operation over an extended
temperature range of –40
°
C to +85
°
C and
supply voltage of 4.5V to 5.5V.
ARCHITECTURE
The core of the PLHS501 is a programmable
fuse array of 72 NAND gates. The output of
each gate folds back upon itself and all other
NAND gates. In this manner, full connectivity
of all logic functions is achieved in the
PLHS501. Any logic function can be created
within the core of the device without wasting
valuable I/O pins. Furthermore, a speed
advantage is acquired by implementing
multi-level logic within a fast internal core
without incurring any delays from the I/O
buffers.
PML is a trademark of Philips Semiconductors
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PLHS501A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable macro logic PML |
| PLHS501I | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable macro logic PML |
| PLHS501IA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable macro logic PML |
| PLHS-WHT-1/2 | 制造商:3M Electronic Products Division 功能描述:Heat Shrink Tubing 1/2in. (12mm) White |
| PLHS-WHT-1/4 | 制造商:3M Electronic Products Division 功能描述:Heat Shrink Tubing 1/4in. (6mm) White |
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