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| 型號(hào)： | PLL1706 |
| 英文描述： | RS232/EIA562/RS485 Transceivers; Package: PDIP; No of Pins: 24; Temperature Range: -40°C to +85°C |
| 中文描述： | 3.3伏雙PLL的多時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 1/17頁(yè) |
| 文件大小： | 128K |
| 代理商： | PLL1706 |
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PLL1705
PLL1706
SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002
3.3-V DUAL PLL MULTICLOCK GENERATOR
FEATURES
27-MHz Master Clock Input
Generated Audio System Clock:
– SCKO0: 768 f
S
(f
S
= 44.1 kHz)
– SCKO1: 384 f
S
, 768 f
S
(f
S
= 44.1 kHz)
– SCKO2: 256 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
– SCKO3: 384 f
S
(f
S
= 32, 44.1, 48, 64, 88.2,
96 kHz)
Zero PPM Error Output Clocks
Low Clock Jitter: 50 ps (Typical)
Multiple Sampling Frequencies:
– f
S
= 32, 44.1, 48, 64, 88.2, 96 kHz
3.3-V Single Power Supply
PLL1705: Parallel Control
PLL1706: Serial Control
Package: 20-Pin SSOP (150 mil), Lead-Free
Product
APPLICATIONS
DVD Players
DVD Add-On Cards for Multimedia PCs
Digital HDTV Systems
Set-Top Boxes
DESCRIPTION
The PLL1705
and PLL1706
are low cost, phase-locked
loop (PLL) multiclock generators. The PLL1705 and
PLL1706 can generate four system clocks from a 27-MHz
reference input frequency. The clock outputs of the
PLL1705 can be controlled by sampling frequency-control
pins and those of the PLL1706 can be controlled through
serial-mode control pins. The device gives customers both
cost and space savings by eliminating external
components and enables customers to achieve the very
low-jitter performance needed for high performance audio
DACs and/or ADCs. The PLL1705 and PLL1706 are ideal
for MPEG-2 applications which use a 27-MHz master
clock such as DVD players, DVD add-on cards for
multimedia PCs, digital HDTV systems, and set-top
boxes.
FUNCTIONAL BLOCK DIAGRAM
Mode Control Interface
( ): PLL1706
XT1
(ML)
SR
(MC)
FS2
(MD)
FS1
CSEL
PLL2
PLL1
OSC
XT2
MCKO1
MCKO2
SCKO0
Divider
Divider
Divider
SCKO1
SCKO2
SCKO3
Reset
Power Supply
VCCAGND VDD1–3 DGND1–3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1706DBQ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1706DBQRG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707 | 制造商:BB 制造商全稱:BB 功能描述:3.3 V DUAL PLL MULTICLOCK GENERATOR |
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