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參數資料
| 型號： | PLL2126X |
| 英文描述： | PLL2126X 20MHz ~ 100MHz FSPLL|Data Sheet |
| 中文描述： | PLL2126X為20MHz?100MHz的FSPLL |數據資料 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 150K |
| 代理商： | PLL2126X |
The
frequency synthesizer. The PLL provides frequency
multiplication capabilities. The output clock frequency
FOUT is related to the input clock frequency FIN by
the following equation:
pll2108x
is
a
Phase
Locked
Loop
(PLL)
FOUT=(m*FIN) / (p*2
s
)
Where FOUT is the output clock frequency. FIN is
the input clock frequency. m, p and s are the values
for programmable dividers. pll2108x consists of a
Phase Frequency Detector(PFD), a Charge Pump, an
Off-chip Loop Filter, a Voltage Controlled Oscillator
(VCO), a 6bit Pre-divider, an 8bit Main-divider and
2bit Post-scaler as shown in functional block diagram.
0.13um CMOS device technology
1.2 Volt single power supply
Output frequency range: 50M ~ 300MHz
Jitter: ±150ps at 300MHz
Duty ratio: 40% to 60% (All tuned range)
Power down mode
Off-chip loop filter
Frequency is changed by programmable divider
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
50MHz ~ 300MHz FSPLL
PLL2108X
NOTE
1.
Don't set the P or M value as zero, that is, seting the P=000000, M=00000000 can cause malfunction of the PLL.
2. The proper range of P and M :
1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range.
4.
Please contact SEC application engineer for proper selection of the P, M, S values of the PLL.
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
Ver 1.3.0. (May. 2002)
FILTER
UP
DN
Pre-Divider
(P)
Main-Divider
(M)
R1
C2
FOUT
FIN
PWRDN
P[5:0]
S[1:0]
Post - Scaler
(S)
(1,2,4,8)
Voltage
Controlled
Oscillator
Phase
Frequency
Detector
Charge
Pump
Fvco/M
Fin/P
Vctrl
Fvco
6b
8b
2b
AVDD12D
AVSS12D
AVDD12A
AVSS12A
VABB
M[7:0]
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