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參數(shù)資料
| 型號： | PLLCORE75 |
| 英文描述： | 12-Bit Rail-to-Rail Micropower DACs in SO-8; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 26K |
| 代理商： | PLLCORE75 |
AMERICAN MICROSYSTEMS, INC
AMI5LG Gate Array
AMI5LS Standard Cell
PLLCORExxx
November 1998
AMI5LG & AMI5LS CMOS
Page 1 of 4
Description
The PLLCORExxx is a phase locked loop building block. This cell contains a voltage
controlled oscillator (VCO), an internal loop filter, and a digital phase frequency
detector. The PLLCORExxx is available in AMI5L standard cells and gate arrays.
Customer supplied delay and divider blocks, as well as an external reference clock, are
required for a complete PLL circuit that will lock a VCO generated clock signal to a
multiple of the reference clock frequency. The clock dividers, delay logic, and test
logic are built of standard cells or gate array core cells as soft megacell blocks.
The ‘xxx’ refers to the center frequency of the VCO.
Features
Internal loop filter saves external loop filter components
Loop filter time constants are pin programmable
Output Duty Cycle of 50% +/- 10%
Specifications
(Vdd = 3.3V +/- 10%,Tj=-55-140c)
CELL
Fmin (MHz)
40
50
60
80
110
Fmax (MHz)
80
100
120
160
220
PLLCORE60
PLLCORE75
PLLCORE90
PLLCORE120
PLLCORE170
Jitter performance data is not yet available. Use of the internal loop filter is expected to
result in jitter perfomance at the 1-3ns level. Use of an external loop filter is expected to
improve the jitter perfomance. Jitter perfomance will depend on the actual ASIC circuit
implementation.
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| PLQ16L8-5A | Dual 12-Bit Rail-to-Rail Micropower DACs; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PLQ16L8-5N | 12-Bit Rail-to-Rail Micropower DAC with Clear Input; Package: PDIP; No of Pins: 8; Temperature Range: -40°C to +85°C |
| PLQ16R4-5A | Fuse-Programmable PLD |
| PLQ16R4-5N | Fuse-Programmable PLD |
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