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參數資料
| 型號： | PLSI1016E-80LJ |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復雜可編程邏輯器件 |
| 文件頁數： | 9/12頁 |
| 文件大小： | 120K |
| 代理商： | PLSI1016E-80LJ |
Specifications
ispLSI 1048
9
USEispLS 1048EAFORNEW
COMMERCAL&INDUSTRAL
ICC can be estimated for the ispLSI 1048 using the following equation:
DESGNS
30
40
50
f
max (MHz)
Notes: Configuration of Twelve 16-bit Counters
Typical Current at 5V, 25
C
Maximum GRP Delay vs GLB Loads
ispLSI 1048-70
ispLSI 1048-50
0126A-48-80-isp
ispLSI 1048-80
2
3
12
16
GLB Loads
G
5
6
7
8
Power Consumption
Power consumption in the ispLSI 1048 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operat-
ing speed.
50
100
150
200
250
20
60
70
I
C
ispLSI 1048
80
0127A-48-80-isp
ICC = 73 + (# of PTs * 0.23) + (# of nets * Max. freq * 0.010) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
Figure 3. Typical Device Power Consumption vs fmax
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