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參數資料
| 型號： | PowerPC 405GP |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32-bit RISC Embedded Controllers(32位RISC結構嵌入式控制器) |
| 中文描述： | 32位RISC嵌入式控制器（32位的RISC結構嵌入式控制器） |
| 文件頁數： | 1/58頁 |
| 文件大小： | 878K |
| 代理商： | POWERPC 405GP |
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PowerPC 405GP Embedded Processor Data Sheet
1
Features
IBM PowerPC
core operating up to 266 MHz
TM
405 32-bit RISC processor
PC-100 Synchronous DRAM (SDRAM)
interface operating up to 133 MHz
- 32-bit interface for non-ECC applications
- 40-bit interface serves 32 bits of data plus 8
check bits for ECC applications
4KB On-chip Memory (OCM)
External Peripheral Bus
- Flash ROM/Boot ROM interface
- Direct support for 8-, 16-, or 32-bit SRAM
and external peripherals
- Up to eight devices
- External Mastering supported
DMA support for external peripherals, internal
UART and memory
- Scatter-gather chaining supported
- Four channels
PCI Revision 2.2 Compliant Interface (32-bit, up
to 66MHz)
- PCI Bus interface can be configured to
operate synchronously or asynchronously
to the chip input clock
- Internal PCI Bus Arbiter which can be
disabled for use with an external arbiter
Ethernet 10/100Mbps (full-duplex) support with
Medium Independent Interface (MII)
Programmable Interrupt Controller supports
interrupts from a variety of sources
- Seven external and 19 internal
- Edge triggered or level-sensitive
- Positive or negative active
- Non-critical or critical interrupt to processor
core
- Programmable critical interrupt priority
ordering
- Programmable critical interrupt vector for
faster vector processing
Programmable Timers
Two serial ports (16550 compatible UART)
One IIC (I
2
C) interface
General Purpose I/O (GPIO) available
Supports JTAG for board level testing
Internal Processor Local Bus (PLB) runs at
SDRAM interface frequency
Supports PowerPC processor boot from PCI
memory
Description
Designed specifically to address embedded
applications, the PowerPC 405GP (PPC405GP)
provides a high-performance, low-power solution
that interfaces to a wide range of peripherals by
incorporating on-chip power management features
and intrinsically lower power dissipation
requirements.
This chip contains a high-performance RISC
processor core, SDRAM controller, PCI bus
interface, Ethernet interface, control for external
ROM and peripherals, DMA with scatter-gather
support, serial ports, IIC interface, and general
purpose I/O.
Technology: IBM CMOS SA12E 0.25
(0.18
μ
m L
eff
)
μ
m
Package: 456-ball (35mm or 27mm), or 413-ball
(25mm) enhanced plastic ball grid array (E-PBGA)
Power (estimated): Typical 1.5W, Maximum 2.0W
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made
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